Motorola MSC8101 ADS User's Guide download pdf (Page 130)

6-22 MSC8101 User’s Guide

DMA Channels

initialized for any of the transfers because the code is not implementing cyclic

buffers.

a. The DMA buffer descriptor 2 address is initialized to an SDRAM memory

location for a 32-bit transfer size, transferring a total of 100 bytes. Once the

buffer descriptor 2 read transfer is complete, it invokes the buffer descriptor 8

transfer.

b. The DMA buffer descriptor 3 address is initialized to another SDRAM

memory location for a 32-bit transfer size, transferring a total of 100 bytes.

Also, BD_ATTR3 must include the next buffer pointer since this is a chained

buffer. DMA channel 3 invokes DMA buffer descriptor 9 once its transfer is

complete.

3. The second DMA transaction is initialized. Since it is a dual-access transaction,

both buffer descriptor 8 and buffer descriptor 9 must be programmed.

a. The buffer descriptor 8 address is initialized to the second SDRAM memory

location for a 32-bit transfer size, reading a total of 100 bytes.

b. The buffer descriptor 9 address is initialized to an internal SRAM memory

location for a 32-bit transfer size, writing a total of 100 bytes. BD_ATTR9

must also enable interrupts so that the SC140 core is notified when the entire

transaction is complete.

4. The DCHCRx for each channel must be initialized. Each DCHCRx value defines

which bus the transaction is occurring on (PowerPC System or PowerPC local

bus), which buffer descriptor is associated with the channel, and the priority level

of the DMA transfer. All of these transactions are internal requests, so none of

them are requested by a peripheral. The DCHCRx registers are programmed for

the first transfer buffer descriptors. Once the first transfer is complete, the

channel remains open, and the second two buffer descriptors define the

remainder of the transfer.

5. Processing begins as soon as the activate channel bit is set in DCHCR2.

Example 6-4. External Flash Memory to External SDRAM Memory, Dual Access Mode

; Memory Map Base Value

SDRAM_LOC equ $20000000 ; SDRAM Base Address

SRAM_LOC equ $02000000 ; SRAM base address on local bus

; Data Addresses

SDRAM_DATA1 equ SDRAM_LOC+$300 ; Location of first SDRAM data

SDRAM_DATA2 equ SDRAM_LOC+$400 ; Location of second SDRAM data

SRAM_DATA equ SRAM_LOC+$4000 ; Location of final data in SRAM

;------------------------------------------------------

MAIN

; Initialize 16 MB SDRAM at address $20000000

INIT_INTER

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Motorola MSC8101 ADS User's Guide Page 130