Programming Sheets
MSC8101 User’s Guide A-21
ELIRB
PIC Edge/Level-Triggered Interrupt Priority Register B
Address: 0x1C08
Reset: 0
Read/Write
0123456789101112131415
PIL62PIL61PIL60PED6PIL72PIL71
001 IPL0 (lowest priority)
000 Interrupts disabled
011 IPL2/IPL3
010 IPL1
101 IPL5
100 IPL4
111 IPL7 (highest priority)
110 IPL6
PIL[70–72, 60–62, 50–52, 40–42] – Priority Level for IRQ Input xx,
Bits 1–3, 5–7, 9–11, 13–15
1 Edge-triggered mode
0 Level-triggered mode
PED[7, 6, 5, 4] – Trigger Mode for IRQ Input xx, Bits 0, 4, 8, 12
PIL70PED7 PED5 PIL50 PIL51 PIL52 PED4 PIL40 PIL41 PIL42
INTERRUPT SCHEME
ELIRA
PIC Edge/Level-Triggered Interrupt Priority Register A
Address: 0x1C00
Reset: 0
Read/Write
0123456789101112131415
PIL22PIL21PIL20PED2PIL32PIL31
001 IPL0 (lowest priority)
000 Interrupts disabled
011 IPL2/IPL3
010 IPL1
101 IPL5
100 IPL4
111 IPL7 (highest priority)
110 IPL6
PIL[30–32, 20–22, 10–12, 0–2] – Priority Level for IRQ Input xx,
Bits 1–3, 5–7, 9–11, 13–15
1 Edge-triggered mode
0 Level-triggered mode
PED[3, 2, 1, 0] – Trigger Mode for IRQ Input xx, Bits 0, 4, 8, 12
PIL30PED3 PED1 PIL10 PIL11 PIL12 PED0 PIL00 PIL01 PIL02
ELIRA
Comments to this Manuals