Motorola MSC8101 ADS User's Guide Page 62

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2-10 MSC8101 User’s Guide
Reset Configuration and Boot
The configuration master first reads a value from address 0x00 and then reads a value
from addresses 0x08, 0x10, and 0x18. These four bytes form the configuration word of the
configuration master, which then proceeds reading the bytes that form the configuration
word of the first slave device. The configuration master drives the whole configuration
word on
D[0–31] and toggles its A0 address line. Each configuration slave uses its RSTCONF
input as a strobe for latching the hard reset configuration word during
HRESET assertion
time. Thus, the first configuration slave whose
RSTCONF input connects to the
configuration master’s
A0 output latches the word driven on D[0–31] as its configuration
word. The configuration master continues to configure all MSC8101 devices in the
system. The configuration master always reads eight configuration words, regardless of
the number of MSC8101 devices in the system.
2.3.2 Reset Configuration Word Values
In the system described in Figure 2-4, one arbiter handles the system bus arbitration and
one memory controller controls the signals and attributes of all memory accesses. Any
MSC8101 in the system can handle the roles of system arbiter and memory controller. The
MSC8101 that serves as a system arbiter uses its internal arbiter, and the rest of the
MSC8101s are configured to work in an external arbitration mode. The MSC8101 that
serves as the memory controller for the system uses its memory controller, and the
remaining MSC8101s are configured to work with an external memory controller. The
arbitration mode and memory controller mode are set in the hard reset configuration word.
Each MSC8101 in the system must have a unique value in the IMMR. In the reset
configuration word, there can be up to eight different values for the first three bits of the
IMMR (ISB[0–2]). Each MSC8101 in the system must be configured to one of these
values. These values can be changed during boot.
MODCK is also configured in reset
configuration to choose the desired clock frequency.
Table 2-6. Configuration EPROM Addresses
Configured Device Byte 0 Address Byte 1 Address Byte 2 Address Byte 3 Address
Configuration master 0x00 0x08 0x10 0x18
First configuration slave 0x20 0x28 0x30 0x38
Second configuration slave 0x40 0x48 0x50 0x58
Third configuration slave 0x60 0x68 0x70 0x78
Fourth configuration slave 0x80 0x88 0x90 0x98
Fifth configuration slave 0xA0 0xA8 0xB0 0xB8
Sixth configuration slave 0xC0 0xC8 0xD0 0xD8
Seventh configuration slave 0xE0 0xE8 0xF0 0xF8
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