Motorola MSC8101 ADS User's Guide download pdf (Page 123)

DMA Programming Examples

DMA Channels 6-15

DREQ[3–4] and DACK[3–4] are multiplexed with IRQ lines on the MSC8101 pins, as shown in

the external signals chapter of the MSC8101 Reference Manual. The remaining DMA

signals are multiplexed on the CPM ports C and D. Since there are four groupings of

DMA signals, up to four external devices can request DMA service via DMA request

lines. However, only two of the devices can use the

DONE/DRACK protocol. Also, if a

system requires use of the

DONE/DRACK signals, then the SCC1:RXD and SCC1:TXD signals

are not available due to multiplexing on the CPM ports. Also, the

DREQ and DACK signals

use the same pins as

BRG7, BRG8, and CLK[7–10]. Therefore, a system designer must use

other baud-rate generators or clocks for the application design.

6.4 DMA Programming Examples

The code examples in this section illustrate how to program the DMA controller in various

modes:

■ A simple buffer to transfer data from internal memory to external memory.

■ Burst mode transactions between two external memory locations. It also uses a

cyclic buffer.

■ A simple buffer to transfer data from an internal peripheral (HDI16) to external

memory.

■ A data transfer between external flash memory, external memory, and internal

memory. The two transfers are chained. This example also shows how interrupts

are used. For an example of a flyby data transfer with an internal peripheral, see

Chapter 9, Enhanced Filter Coprocessor (EFCOP).

The examples in this section use equate labels for the location of the DMA registers and

buffer descriptors. It is assumed that these equates are declared before the example code.

Equate labels include the register or field name preceded with “M_”.

6.4.1 Internal to External Dual Access, Simple Buffer

Example 6-1 uses a DMA channel to transfer data from internal to external memory with

a simple buffer. Since data is transferred from internal memory to external SDRAM, the

DMA transfer is a dual transaction. A transaction transfers SIZE bytes of data 32-bits at a

time. Bank 2 and bank 10 of the memory controller are configured to allow the DMA

channel to access external memory through the SDRAM and the internal DSP SRAM

through the UPMC, respectively. The memory buffer to which the OUT_ADDR equate

points must be within the memory range of bank 2; the memory buffer to which the

IN_ADDR equate points must be within the memory range of bank 10.

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Motorola MSC8101 ADS User's Guide Page 123