Contents
xii MSC8101 User’s Guide
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MSC8101 USER’S GUIDE
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How to reach us:
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1-303-675-2140
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1-800-441-2447
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Chapter 5
7
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Chapter 11
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Chapter 12
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EOnCE/JTAG
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Contents
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MSC8101 User’s Guide xi
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MSC8101 User’s Guide xiii
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MSC8101 User’s Guide xv
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MSC8101 User’s Guide xvii
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About This Book
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Audience and Helpful Hints
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Organization
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Other MSC8101 Documentation
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Further Reading
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Chapter 1
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MSC8101 Overview
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1.2 Features
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1.2.2 On-Device Memories
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1.2.5 System Interface Unit
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1.2.6 On-Device Peripherals
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1.2.7 DMA Engine
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1.3 Architecture
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1.3.2 SRAM
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1-8 MSC8101 User’s Guide
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Extended Core
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1.3.4 DMA Controller
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Offset 0123456789101112131415
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0x0 Status and Control
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0x2 Data Length
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0x4 High-Order Buffer Pointer
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0x6 Low-Order Buffer Pointer
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MSC8101 Reference Manual
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Architecture
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MSC8101 Overview 1-15
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Table 1-6. SCC Parameter RAM
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MSC8101 Overview 1-17
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1-18 MSC8101 User’s Guide
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MSC8101 Overview 1-19
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1-20 MSC8101 User’s Guide
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Centralized DSP Architecture
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MSC8101 Application Examples
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MSC8101 Overview 1-25
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Serial Backplane
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1.5 Software Development
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Software Development
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MSC8101 Overview 1-27
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1-28 MSC8101 User’s Guide
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Chapter 2
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Reset Configuration and Boot
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2.1.1 Bootloader Program
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2.1.2 Clocks
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Connected
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Address Bus
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Data Bus
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BTM[0–1]/EE[4–5]
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Host Port
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2-16 MSC8101 User’s Guide
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2.5 Related Reading
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2-18 MSC8101 User’s Guide
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Chapter 3
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3.2 Partitioning Memory
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3.3 Allocating Memory
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3.5 Related Reading
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3-6 MSC8101 User’s Guide
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Chapter 4
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Memory-Mapped Devices
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4.2 External Bus Basics
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AM29LV160D
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2MB Flash
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01234 0567 9EHTR8
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01234 05678910
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Table 4-1. GPCM ORx Settings
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READ, WRITE, and PRECHARGE
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ACTIVATE command
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4-10 MSC8101 User’s Guide
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CAS latency = 2, Last Data
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4-12 MSC8101 User’s Guide
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Multiplex
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4-14 MSC8101 User’s Guide
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GPL2 is programmed high in a
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CSx = HCS
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4.6 Related Reading
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4-20 MSC8101 User’s Guide
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System and Local Buses
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5.1 PowerPC System Bus
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PowerPC System Bus
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QBus Switch
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5.2 PowerPC Local Bus
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5.3 Bus Interaction
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Figure 5-6. Bus Architecture
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5.3.1 DMA Controller
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5.3.2 SDMA Channels
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Figure 5-8. SDMA Data Paths
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5.4 Related Reading
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5-12 MSC8101 User’s Guide
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Chapter 6
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DMA Channels
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6.1.1 Operating Modes
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6.1.2 Transfer Types
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External
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6.2 Initializing the DMA
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Table 6-2. DCHCRx Bits
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Table 6-3. DCPRAM Addressing
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6-10 MSC8101 User’s Guide
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6.2.6 FIFO Requests
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6.2.9 Interrupts
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These signals are:
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(DMA request)
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(DMA acknowledge)
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6-16 MSC8101 User’s Guide
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from the vector base
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6.6 Related Reading
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Chapter 7
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PERIPH_IR
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7.3.4 Routing Interrupts
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0x0 TRAP
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7.4.1 PIC Programming
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7.4.4 PIC Macros
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Chapter 8
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Host Interface (HDI16)
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8.1.1 Host-Side Model
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8.1.2 DSP-Side Model
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8.2.1 Normal Mode
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8-6 MSC8101 User’s Guide
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8.2.2 Host DMA Mode
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Host Interface (HDI16) 8-9
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HDM0 is
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HPCR[15]:OAD Data Valid
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0 HACK pin is asserted
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Figure 8-3
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8-12 MSC8101 User’s Guide
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8.3.1 Software Polling
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8.3.2 DSP Interrupts
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Table 8-16. PIC Interrupts
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Host Interface (HDI16) 8-17
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8.3.3 Host Requests
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Host Interface (HDI16) 8-19
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Host Interface (HDI16) 8-21
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8-22 MSC8101 User’s Guide
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Host Interface (HDI16) 8-23
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8.5 Related Reading
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Chapter 9
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9-2 MSC8101 User’s Guide
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9-4 MSC8101 User’s Guide
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9.2.2 Complex Mode
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9.2.4 Magnitude Mode
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9-8 MSC8101 User’s Guide
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9.4.1 Rounding
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9-10 MSC8101 User’s Guide
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9.5.1 Polling
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9.5.2 Interrupts
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9.5.3 DMA
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9.6 Programming Examples
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FCNT/2 complex
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9-20 MSC8101 User’s Guide
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FDOR_ADDR, is written to the
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NSAMP/4 data samples are
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Programming Examples
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9.7 Related Reading
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9-26 MSC8101 User’s Guide
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Chapter 10
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10.1.2 Driver Memory Map
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10.1.3 Memory Usage
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× 64 Kbps slots
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10-8 MSC8101 User’s Guide
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Figure 10-7. Loopback Modes
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× 8), thus creating a
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10.3 Configure the Channels
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0x3800 is used
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10-14 MSC8101 User’s Guide
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CLK15 pin
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BRG50 pin must be
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10.6 Related Reading
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11.2 Setting the Clock
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11-4 MSC8101 User’s Guide
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Operating the SPI as a Master
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Figure 11-3. SPI as a Master
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11-8 MSC8101 User’s Guide
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Figure 11-4. SPI as Slave
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Operating the SPI as a Slave
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11.7 Related Reading
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11-14 MSC8101 User’s Guide
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12-2 MSC8101 User’s Guide
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12.1.1 Instructions
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12-4 MSC8101 User’s Guide
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12.1.3 Registers
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12-6 MSC8101 User’s Guide
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EOnCE/JTAG Basics
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EOnCE/JTAG 12-7
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12-8 MSC8101 User’s Guide
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EOnCE/JTAG 12-9
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12.1.3.1 CORE_CMD Example 1
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12.1.3.2 CORE_CMD Example 2
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12.1.3.3 CORE_CMD Example 3
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EOnCE/JTAG 12-11
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12-12 MSC8101 User’s Guide
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EOnCE/JTAG 12-13
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12-14 MSC8101 User’s Guide
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Figure 12-8. Writing to ERCV
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12.7 Downloading Software
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Downloading Software
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EOnCE/JTAG 12-17
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12-18 MSC8101 User’s Guide
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EOnCE/JTAG 12-19
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12.10 Counting Core Cycles
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Counting Core Cycles
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EOnCE/JTAG 12-21
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12.11 Related Reading
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Appendix A
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Programming Reference
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A-2 MSC8101 User’s Guide
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MSC8101 User’s Guide A-3
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A-4 MSC8101 User’s Guide
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MSC8101 User’s Guide A-5
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A-6 MSC8101 User’s Guide
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A.2 Programming Sheets
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SYSTEM INTERFACE UNIT
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Address: 0x10240
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Reset: 0
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Read/Write
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Address: 0x10220
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MEMORY CONTROLLER
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BR[0–7, 10, 11]
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OR[0–7, 10, 11]
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MAMR, MBMR, MCMR
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INTERRUPT SCHEME
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SICR/SICR_EXT
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SIEXR/SIEXR_EXT
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DIRECT MEMORY ACCESS
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DCHCR[0–15]
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ENHANCED FILTER
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COPROCESSOR
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Address: 0x0C80
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Host Control Register
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Address: 0x0000
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Hardware Reset: 0
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HCR (HICR=1)
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HOST INTERFACE
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Host Port Control Register
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Address: 0x0020
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ICR (DMA=0, DMA=1, HICR=0)
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ICR (DMA=0, DMA=1, HICR=1)
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Appendix B
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Glossary
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Glossary Appendix B-3
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Debug mode
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DSP MIPs
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Glossary Appendix B-7
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FC-PBGA
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Glossary Appendix B-9
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Glossary Appendix B-11
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Glossary Appendix B-13
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TXD, RXD, and SMSYN
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Glossary Appendix B-15
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Glossary Appendix B-17
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Appendix C
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Bootloader Program
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0x80
310
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0
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0x100
310
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0x180
310
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long instead of bytes
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C-16 MSC8101 User’s Guide
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Appendix D
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Acronyms and Abbreviations
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D-2 MSC8101 User’s Guide
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Flip Chip-Plastic Ball Grid
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Array package
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D-4 MSC8101 User’s Guide
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MSC8101 User’s Guide D-5
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D-6 MSC8101 User’s Guide
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MSC8101 User’s Guide D-7
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D-8 MSC8101 User’s Guide
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MSC8101 User’s Guide D-9
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D-10 MSC8101 User’s Guide
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Numerics
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, 1-4, 1-22, 4-2, 5-3
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SET command 4-7
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-ALL-BANKS command 4-7
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, 10-1, 10-8
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