Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee reg
Device User Guide — 9S12C128DGV1/D V01.1110
Device User Guide — 9S12C128DGV1/D V01.11100beyond the power supply levels that it ties to. If the input level goes outside of this range it will effe
Device User Guide — 9S12C128DGV1/D V01.11101B.4.3.3 Current injectionThere are two cases to consider.1. A current is injected into the channel being
Device User Guide — 9S12C128DGV1/D V01.11102B.4.4 ATD accuracy (5V Range)Table B-6 specifies the ATD conversion performance excluding any errors due
Device User Guide — 9S12C128DGV1/D V01.11103For the following definitions see also Figure B-2.Differential Non-Linearity (DNL) is defined as the diffe
Device User Guide — 9S12C128DGV1/D V01.11104Figure B-2 ATD Accuracy DefinitionsNOTE: Figure B-2 shows only definitions, for specification values refe
Device User Guide — 9S12C128DGV1/D V01.11105B.5 NVM, Flash and EEPROMB.5.1 NVM timingThe time base for all NVM program or erase operations is derive
Device User Guide — 9S12C128DGV1/D V01.11106B.5.1.3 Sector EraseErasing either a 512 byte or 1024 byte Flash sector takes:The setup times can be igno
Device User Guide — 9S12C128DGV1/D V01.11107B.5.2 NVM ReliabilityThe reliability of the NVM blocks is guaranteed by stress test during qualification,
Device User Guide — 9S12C128DGV1/D V01.11108
Device User Guide — 9S12C128DGV1/D V01.11109B.6 Reset, Oscillator and PLLThis section summarizes the electrical characteristics of the various startu
Device User Guide — 9S12C128DGV1/D V01.1111List of FiguresFigure 0-1 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device User Guide — 9S12C128DGV1/D V01.11110B.6.1.4 External ResetWhen external reset is asserted for a time greater than PWRSTL the CRG module gener
Device User Guide — 9S12C128DGV1/D V01.11111oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure isasser
Device User Guide — 9S12C128DGV1/D V01.11112Figure B-3 Basic PLL functional diagramThe following procedure can be used to calculate the resistance an
Device User Guide — 9S12C128DGV1/D V01.11113And finally the frequency relationship is defined asWith the above values the resistance can be calculated
Device User Guide — 9S12C128DGV1/D V01.11114Figure B-4 Jitter DefinitionsThe relative deviation of tnomis at its maximum for one clock period, and de
Device User Guide — 9S12C128DGV1/D V01.11115This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate
Device User Guide — 9S12C128DGV1/D V01.11116
Device User Guide — 9S12C128DGV1/D V01.11117B.7 MSCANTable B-13 MSCAN Wake-up Pulse CharacteristicsConditions are shown in Table A-4 unless otherwi
Device User Guide — 9S12C128DGV1/D V01.11118
Device User Guide — 9S12C128DGV1/D V01.11119B.8 SPIAppendix C Electrical SpecificationsThis section provides electrical parametrics and ratings for
Device User Guide — 9S12C128DGV1/D V01.1112Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) . . . . . . 130Figure 19-1 Pin Assi
Device User Guide — 9S12C128DGV1/D V01.11120Figure C-2 SPI Master Timing (CPHA=1)In Table C-2 the timing characteristics for master mode are listed.T
Device User Guide — 9S12C128DGV1/D V01.11121C.2 Slave ModeIn Figure C-3 the timing diagram for slave mode with transmission format CPHA=0 is depicted
Device User Guide — 9S12C128DGV1/D V01.11122Figure C-4 SPI Slave Timing (CPHA=1)In Table C-3 the timing characteristics for slave mode are listed.Tab
Device User Guide — 9S12C128DGV1/D V01.11123C.3 External Bus TimingA timing diagram of the external multiplexed-bus is illustrated in Figure C-5 with
Device User Guide — 9S12C128DGV1/D V01.11124Table C-4 Expanded Bus Timing Characteristics (5V Range)Conditions are 4.75V < VDDX < 5.25V, Junct
Device User Guide — 9S12C128DGV1/D V01.11125Table C-5 Expanded Bus Timing Characteristics (3.3V Range)Conditions are VDDX=3.3V+/-10%, Junction Tempe
Device User Guide — 9S12C128DGV1/D V01.11126
Device User Guide — 9S12C128DGV1/D V01.11127Appendix D Package InformationD.1 GeneralThis section provides the physical dimensions of the MC9S12C Fa
Device User Guide — 9S12C128DGV1/D V01.11128D.2 80-pin QFP packageFigure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)NOTES:1. DIMENSIONING A
Device User Guide — 9S12C128DGV1/D V01.11129D.3 52-pin LQFP packageFigure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)FNOTES:1. DIMENSIO
Device User Guide — 9S12C128DGV1/D V01.1113List of TablesTable 0-1 List of MC9S12C and MC9S12GC Family members. . . . . . . . . . . . . . . . . . . .
Device User Guide — 9S12C128DGV1/D V01.11130D.4 48-pin LQFP packageFigure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)AA1Z0.200 AB
Device User Guide — 9S12C128DGV1/D V01.11131Appendix E Emulation InformationE.1 GeneralIn order to emulate the MC9S12C and 9S12GC-Family devices, ex
Device User Guide — 9S12C128DGV1/D V01.11132E.1.1 PK[2:0] / XADDR[16:14]PK2-PK0 provide the expanded address XADDR[16:14] for the external bus.Refer
Device User Guide — 9S12C128DGV1/D V01.11133E.2 112-pin LQFP packageFigure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanica
Device User Guide — 9S12C128DGV1/D V01.11134
Device User Guide — 9S12C128DGV1/D V01.11135Device User Guide End Sheet
Device User Guide — 9S12C128DGV1/D V01.11136FINAL PAGE OF136PAGES
Device User Guide — 9S12C128DGV1/D V01.1114$0240 - $027F PIM (Port Interface Module) 47$0280 - $03FF Reserved space 50Table 1-3 Assigned Part ID Numbe
Device User Guide — 9S12C128DGV1/D V01.1115Table C-3 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device User Guide — 9S12C128DGV1/D V01.1116
Device User Guide — 9S12C128DGV1/D V01.1117PrefaceThe Device User Guide provides information about the MC9S12C-Family as well the MC9S12GC-Familydevic
Device User Guide — 9S12C128DGV1/D V01.1118Figure 0-1 Order Part number CodingTable 0-2 MC9S12C-Family Part Number CodingPart NumberMask1setTemp. Pa
Device User Guide — 9S12C128DGV1/D V01.1119MC9S12C96CPB XL09S -40˚C, 85˚C 52LQFP 25MHz C128 die 96K 4K 35MC9S12C96CFU XL09S -40˚C, 85˚C 80QFP 25MHz
Device User Guide — 9S12C128DGV1/D V01.112Revision HistoryVersionNumberRevisionDateEffectiveDateAuthor Description of Changes00.01 25.JAN.03 25.JAN.03
Device User Guide — 9S12C128DGV1/D V01.1120Table 0-3 MC9S12GC-Family Part Number CodingNOTES:1. XL09S denotes all minor revisions of L09S masksetXL45
Device User Guide — 9S12C128DGV1/D V01.1121Table 0-4 Document ReferencesMC9S12GC32MFU xL45J / xM34C -40˚C, 125˚C 80QFP 25MHz C32 die 32K 2K 60MC9S1
Device User Guide — 9S12C128DGV1/D V01.1122TerminologyAcronyms and AbbreviationsNew or invented terms, symbols, and notations
Device User Guide — 9S12C128DGV1/D V01.1123Section 1 Introduction1.1 OverviewThe MC9S12C-Family and the MC9S12GC-Family is a 48/52/80 pin Flash-base
Device User Guide — 9S12C128DGV1/D V01.1124– 1K, 2K or 4K Byte RAM• Analog-to-Digital Converters– One 8-channel module with 10-bit resolution.– Extern
Device User Guide — 9S12C128DGV1/D V01.1125– Pierce or low current Colpitts oscillator– Phase-locked loop clock frequency multiplier– Limp home mode i
Device User Guide — 9S12C128DGV1/D V01.1126– Special Single-Chip Mode with active Background Debug Mode– Special Test Mode (Motorola use only)– Specia
Device User Guide — 9S12C128DGV1/D V01.11271.4 Block DiagramFigure 1-1 MC9S12C-Family Block DiagramMSCANTXCANRXCAN16K, 32K, 64K, 96K, 128K Byte Flash
Device User Guide — 9S12C128DGV1/D V01.11281.5 Device Memory MapTable 1-1 shows the device register map of the MC9S12C-Family after reset. The follow
Device User Guide — 9S12C128DGV1/D V01.1129Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map$0000$FFFF$C000$8000$4000$0400$FF00EXTNO
Device User Guide — 9S12C128DGV1/D V01.11301.07 14.SEP.04 14.SEP.04Removed LVRD from electrical parameter Table B-1.Removed fosc from Table A-4. (Cove
Device User Guide — 9S12C128DGV1/D V01.1130Figure 1-3 MC9S12C96 and MC9S12GC96 User Configurable Memory Map$0000$FFFF$C000$8000$4000$0400$FF00EXTNORM
Device User Guide — 9S12C128DGV1/D V01.1131Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map$0000$FFFF$C000$8000$4000$0400$FF00EXTNORM
Device User Guide — 9S12C128DGV1/D V01.1132Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map$0000$FFFF$C000$8000$4000$0400$FF00EXTNORM
Device User Guide — 9S12C128DGV1/D V01.1133Figure 1-6 MC9S12GC16 User Configurable Memory Map1.6 Detailed Register MapThe detailed register map of t
Device User Guide — 9S12C128DGV1/D V01.1134$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)Address Name Bit 7 Bit 6 Bit 5 Bit
Device User Guide — 9S12C128DGV1/D V01.1135$0018 - $0018 Miscellaneous Peripherals (Device User Guide)$0019 - $0019 VREG3V3 (Voltage Regulator)$0012 I
Device User Guide — 9S12C128DGV1/D V01.1136$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control,
Device User Guide — 9S12C128DGV1/D V01.1137$002CDBGCAL readBit 7 654321Bit 0BKP0L write$002DDBGCBX readPAGSEL EXTCMPBKP1X write$002EDBGCBH readBit 15
Device User Guide — 9S12C128DGV1/D V01.1138$0040 - $006F TIM (Timer 16 Bit 8 Channels)$003B RTICTLRead: 0RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0Write:$003C
Device User Guide — 9S12C128DGV1/D V01.1139$0050 TC0 (hi)Read:Bit 15 14 13 12 11 10 9 Bit 8Write:$0051 TC0 (lo)Read:Bit 7 654321Bit 0Write:$0052 TC1 (
Device User Guide — 9S12C128DGV1/D V01.114
Device User Guide — 9S12C128DGV1/D V01.1140$0070 - $007F Reserved$0068 ReservedRead: 00000000Write:$0069 ReservedRead: 00000000Write:$006A ReservedRea
Device User Guide — 9S12C128DGV1/D V01.1141$00A0 - $00C7 Reserved$008B ATDSTAT1Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0Write:$008C ReservedRead:
Device User Guide — 9S12C128DGV1/D V01.1142$00D0 - $00D7 Reserved$00C8 - $00CF SCI (Asynchronous Serial Interface)Address Name Bit 7 Bit 6 Bit 5 Bit 4
Device User Guide — 9S12C128DGV1/D V01.1143$00E0 - $00FF PWM (Pulse Width Modulator)Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0$00E0
Device User Guide — 9S12C128DGV1/D V01.1144$00F7 PWMPER5Read:Bit 7 6 5 4 3 2 1 Bit 0Write:$00F8 PWMDTY0Read:Bit 7 6 5 4 3 2 1 Bit 0Write
Device User Guide — 9S12C128DGV1/D V01.1145$0110 - $013F Reserved$010C ReservedRead: 00000000Write:$010D ReservedRead: 00000000Write:$010E ReservedRea
Device User Guide — 9S12C128DGV1/D V01.1146Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout$014E CANRXERRRead:RXERR7 RXERR6 RXE
Device User Guide — 9S12C128DGV1/D V01.1147$0180 - $023F Reserved$0240 - $027F PIM (Port Interface Module)$xx11Extended ID Read:ID20 ID19 ID18 SRR=1 I
Device User Guide — 9S12C128DGV1/D V01.1148$0249 PTISRead: 0000PTIS3 PTIS2 PTIS1 PTIS0Write:$024A DDRSRead: 0000DDRS3 DDRS2 DDRS1 DDRS0Write:$024B RDR
Device User Guide — 9S12C128DGV1/D V01.1149$0261 ReservedRead: 00000000Write:$0262 ReservedRead: 00000000Write:$0263 ReservedRead: 00000000Write:$0264
Device User Guide — 9S12C128DGV1/D V01.115Table of ContentsSection 1 Introduction1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device User Guide — 9S12C128DGV1/D V01.11501.7 Part ID AssignmentsThe part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A
Device User Guide — 9S12C128DGV1/D V01.1151MC9S12C32, MC9S12GC32MEMSIZ0 $00MEMSIZ1 $80MC9S12C64, MC9S12GC64MEMSIZ0 $01MEMSIZ1 $C0MC9S12C96,MC9S12GC96M
Device User Guide — 9S12C128DGV1/D V01.1152Section 2 Signal Description2.1 Device PinoutFigure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family1234
Device User Guide — 9S12C128DGV1/D V01.1153Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-FamilyMC9S12C-FamilyMC9S12GC-Family123456789101112133938
Device User Guide — 9S12C128DGV1/D V01.1154Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-FamilyMC9S12C-FamilyMC9S12GC-Family123456789101112363534
Device User Guide — 9S12C128DGV1/D V01.11552.2 Signal Properties SummaryTable 2-1 Signal PropertiesPin NameFunction 1Pin NameFunction 2Pin NameFunct
Device User Guide — 9S12C128DGV1/D V01.11562.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versionsNot Bonded Pins If the port pins are no
Device User Guide — 9S12C128DGV1/D V01.11572.3 Detailed Signal Descriptions2.3.1 EXTAL, XTAL — Oscillator PinsEXTAL and XTAL are the crystal driver
Device User Guide — 9S12C128DGV1/D V01.11582.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode PinThe BKGD / TAGHI / MODC pin is used a
Device User Guide — 9S12C128DGV1/D V01.1159Figure 2-5 Colpitts Oscillator Connections (PE7=1)Figure 2-6 Pierce Oscillator Connections (PE7=0)Figure
Device User Guide — 9S12C128DGV1/D V01.1162.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device User Guide — 9S12C128DGV1/D V01.11602.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6PE6 is a general purpose input or output pin. It is used as a
Device User Guide — 9S12C128DGV1/D V01.11612.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt PinThe IRQ input provides a means of applying
Device User Guide — 9S12C128DGV1/D V01.11622.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0]PP[5:0] are general purpose input or output pin
Device User Guide — 9S12C128DGV1/D V01.11632.3.27 PS[3:2] — Port S I/O Pins [3:2]PS3 and PS2 are general purpose input or output pins. These pins are
Device User Guide — 9S12C128DGV1/D V01.11642.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREGVDDA, VSSA are the power supply and ground input pins
Device User Guide — 9S12C128DGV1/D V01.1165The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.F
Device User Guide — 9S12C128DGV1/D V01.1166latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the
Device User Guide — 9S12C128DGV1/D V01.1167of this is the user downloads a key through the SCI which allows access to a programming routine thatupdate
Device User Guide — 9S12C128DGV1/D V01.11684.4.1 StopExecuting the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in
Device User Guide — 9S12C128DGV1/D V01.11695.3 ResetsResets are a subset of the interrupts featured inTable 5-1. The different sources capable of gen
Device User Guide — 9S12C128DGV1/D V01.1175.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device User Guide — 9S12C128DGV1/D V01.1170changed to known start-up states. Refer to the respective module Block User Guides for register resetstates
Device User Guide — 9S12C128DGV1/D V01.1171For all devices Flash Page 3F is visible in the $C000-$FFFF range if ROMON is set. For all devices (ecept9S
Device User Guide — 9S12C128DGV1/D V01.1172To prevent unnecessary current flow in production package options, the states of DDRK and PUPKEshould not b
Device User Guide — 9S12C128DGV1/D V01.1173Table 8-1 Recommended External Component ValuesComponent Purpose Type ValueC1 VDD1 filter capapcitor cerami
Device User Guide — 9S12C128DGV1/D V01.1174Figure 8-1 Recommended PCB Layout (48 LQFP)C5C4C1C6C3C8C7Q1C10C9R1VDDXVSSXVDDRVSSRVDD1VSS1VDDPLLVSSPLLVDDA
Device User Guide — 9S12C128DGV1/D V01.1175)Figure 8-2 Recommended PCB Layout (52 LQFP)C4C1C6C8C7Q1C10C9R1VDDXVSSXVDDRVSSRVDD1VSS1VDDPLLVSSPLLVDDAVSS
Device User Guide — 9S12C128DGV1/D V01.1176)Figure 8-3 Recommended PCB Layout (80 QFP)VDDAC5C4C8C7Q1C10C9R1VDDRVSSRVDDPLLVSSPLLC11C6C3VDDXVSSXVSSAC1V
Device User Guide — 9S12C128DGV1/D V01.1177Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce OscillatorC4C1C6VDDXVSSXVDDRVSSRVDD1VSS1VDDAVSSAC3C5C
Device User Guide — 9S12C128DGV1/D V01.1178Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce OscillatorC4C1C6VDDXVSSXVDDRVSSRVDD1VSS1VDDAVSSAC3C5C
Device User Guide — 9S12C128DGV1/D V01.1179Figure 8-6 Recommended PCB Layout for 80QFP Pierce OscillatorSection 9 Clock Reset Generator (CRG) Block
Device User Guide — 9S12C128DGV1/D V01.118Section 16 RAM Block DescriptionSection 17 Pulse Width Modulator (PWM) Block DescriptionSection 18 MSCAN Bl
Device User Guide — 9S12C128DGV1/D V01.11809.1 Device-specific informationThe Low Voltage Reset feature uses the low voltage reset signal from the VR
Device User Guide — 9S12C128DGV1/D V01.1181Consult the SCI Block User Guide for information about the Asynchronous Serial CommunicationsInterface modu
Device User Guide — 9S12C128DGV1/D V01.1182Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.This module is no
Device User Guide — 9S12C128DGV1/D V01.1183Appendix A Electrical CharacteristicsA.1 GeneralNOTE:The electrical characteristics given in this section
Device User Guide — 9S12C128DGV1/D V01.1184VSS1 and VSS2 are internally connected by metal.VDD1 and VDD2 are internally connected by metal.VDDA, VDDX,
Device User Guide — 9S12C128DGV1/D V01.1185A.1.5 Absolute Maximum RatingsAbsolute maximum ratings are stress ratings only. A functional operation und
Device User Guide — 9S12C128DGV1/D V01.1186A.1.6 ESD Protection and Latch-up ImmunityAll ESD testing is in conformity with CDF-AEC-Q100 Stress test q
Device User Guide — 9S12C128DGV1/D V01.1187NOTE:Instead of specifying ambient temperature all parameters are specified for the moremeaningful silicon
Device User Guide — 9S12C128DGV1/D V01.11881. Internal Voltage Regulator disabledWhich is the sum of all output currents on I/O ports associated with
Device User Guide — 9S12C128DGV1/D V01.1189Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.A.1.9 I/O Characteristi
Device User Guide — 9S12C128DGV1/D V01.119B.6 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device User Guide — 9S12C128DGV1/D V01.1190Table A-6 5V I/O CharacteristicsConditions are 4.5< VDDX <5.5V Termperature from -40˚C to +140˚C, u
Device User Guide — 9S12C128DGV1/D V01.1191Table A-7 3.3V I/O CharacteristicsConditions are VDDX=3.3V +/-10%, Termperature from -40˚C to +140˚C, u
Device User Guide — 9S12C128DGV1/D V01.1192A.1.10 Supply CurrentsThis section describes the current consumption characteristics of the device as well
Device User Guide — 9S12C128DGV1/D V01.1193Table A-8 Supply Current Characteristics for MC9S12C32Conditions are shown in Table A-4 with internal regu
Device User Guide — 9S12C128DGV1/D V01.1194Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128Conditions are shown in Table A
Device User Guide — 9S12C128DGV1/D V01.1195Appendix B Electrical SpecificationsB.1 Voltage Regulator Operating ConditionsTable B-1 Voltage Regulat
Device User Guide — 9S12C128DGV1/D V01.1196B.2 Chip Power-up and LVI/LVR graphical explanationVoltage regulator sub modules LVI (low voltage interrup
Device User Guide — 9S12C128DGV1/D V01.1197B.3.2 Capacitive LoadsThe capacitive loads are specified in Table B-2. Ceramic capacitors with X7R dielect
Device User Guide — 9S12C128DGV1/D V01.1198
Device User Guide — 9S12C128DGV1/D V01.1199B.4 ATD CharacteristicsThis section describes the characteristics of the analog to digital converter.VRL i
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