1-2 MSC8101 User’s Guide
MSC8101 Overview
(ATM, Ethernet, IP). The MSC8101 performs digital signal processing tasks such
as speech compression, echo cancellation, fax or modem data pump, error
correction/data compression (ECDC), or even real-time protocol (RTP).
Furthermore, the MSC8101 performs the network interface task (using the CPM),
thus removing bottlenecks in these systems.
1.2 Features
The following sections give an overview of MSC8101 features.
1.2.1 High-performance StarCore SC140 Core
■ Up to 1200 true DSP MIPS or 3000 RISC MIPS with a 300 MHz clock at 1.5 V
core voltage, where a true DSP MIPS is a multiply-accumulate (MAC) operation
plus the associated MOVEs and pointers update
■ Estimated power dissipation of 0.13 mA/DSP MIPS @ 1.5 V (234 mW) for core
running from internal memory
■ Four 16-bit arithmetic logic units (ALUs), each with a 40-bit parallel barrel shifter
■ Two address arithmetic units (AAUs) with integer arithmetic capabilities and
unique DSP addressing modes
■ 32-bit data and program address space
■ Sixteen 40-bit wide data registers
■ Eight 32-bit wide address pointer registers, eight 32-bit wide bus address registers,
four 32-bit wide offset registers, and four 32-bit wide modifier registers
■ Two 32-bit wide stack pointers: user stack pointer and supervisor stack pointer
■ Hardware support for fractional and integer data types
■ Very rich 16-bit wide orthogonal instruction set
■ Up to 6 instructions executed in a single clock cycle
■ Variable-Length Execution Set (VLES) execution model, optimized for
performance and code density
■ Zero overhead hardware DO loops
■ Single unified memory space with byte addressability
■ Position independent code (PIC) support
■ IEEE 1149.1-compatible JTAG port
■ Enhanced On-Chip Emulation (EOnCE) module with real-time debugging
capability
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