Motorola MSC8101 ADS User's Guide download pdf (Page 172)

8-20 MSC8101 User’s Guide

Host Interface (HDI16)

The request signal lines from the DSP normally connect to the host’s interrupt request pins

(

IRQx), which generate an interrupt in the host. Generally, the host interrupt service routine

must test the status bits in the HDI16 host-side ISR to determine the interrupt source. To

clear the interrupt request, the host must read or write the appropriate HDI16 host-side

data registers, TX[0–3] and RX[0–3].

8.3.4 Direct Memory Access (DMA)

Two distinct DMA mechanisms are associated with the HDI16: external DMA and

internal DMA. Externally, the host or an external DMA controller connected to the HDI16

host bus can transfer data between itself and the HDI16 port. External DMA operation is

described in Section 8.2.2, Host DMA Mode, on page 8-8. The DMA controller that is

internal to the DSP is the subject of this section.

The MSC8101 DMA controller performs data transfers between memory (either external

on the PowerPC system bus or internal) and the HDI16 HORX and HOTX data registers

with no SC140 core intervention. The DMA controller frees the core to use its processing

power on functions other than polling or interrupt routines associated with the HDI16.

DMA may well be the most efficient and least costly method to use for data transfers, but

it requires available DMA channels. If the HDI16 DMA controller transfers data to and

from the on-device SRAM, a single DMA channel can be used in flyby mode.

If the

source or destination is on the PowerPC system bus, two DMA channels are required, one

to transfer data between the PowerPC memory and the DMA FIFO and the other to

transfer the data between the HDI16 data register and the DMA FIFO.

Table 8-19. HTRQ and HRRQ Pins In Double Request Mode (ICR[13]:HDRQ=1)

ICR[14]=TREQ ICR[15]=RREQ HTRQ Pin HRRQ Pin

0 0 No interrupts No interrupts

0 1 No interrupts ISR[15]:RXDF request enabled

1 0 ISR[14]:TXDE Request enabled No interrupts

1 1 ISR[14]:TXDE Request enabled ISR[15]:RXDF request enabled

1. A flyby transfer is also known as a “single access data transaction.” The data path is between a peripheral

and memory with the same port size, located on the same bus. On the MSC8101, flyby transactions can

occur only between external peripherals and external memories located on the PowerPC bus, or between

internal peripherals and internal SRAM located on the local bus. Flyby operations do not require access

to the DMA FIFO.

1 2 ... 167 168 169 170 171 172 173 174 175 176 177 ... 345 346

No comments

Motorola MSC8101 ADS User's Guide Page 172