Motorola MSC8101 ADS User's Guide download pdf (Page 193)

Programming Examples

Enhanced Filter Coprocessor (EFCOP) 9-17

uses Adaptive mode and the data output not empty interrupt (IRQ3) to update the

coefficients as shown in Section 9.2.1.1, as follows:

1. Address register pointers are initialized for the filter input and output data (

INPUT

and

OUTPUT).

2. The EFCOP control parameters are written to the appropriate memory mapped

control registers as follows:

a. FDM and FCM are located at the beginning of the shared memory, so the

FDBA and FCBA registers are written with zero.

b. The

FCNT constant defines the filter length and is equal to the number of real

filter coefficients.

FCNT - 1 is written to the filter count register.

c. The value 0x2105 is written to the control register to enable the EFCOP in real

FIR filter mode with Adaptive mode enabled and data and coefficient

initialization enabled. This value also enables the Data Output Not Empty

(

IRQ3) interrupt.

3. The code enables interrupts as follows:

a. The appropriate bits in the core control registers are set. The interrupt mask bits

(I0–2) of the SR are cleared to permit all interrupt priority levels.

b. The value 0x7000 is written to the ELIRA. This value sets the PIL[30–32] bits

to assign

IRQ3 with a priority level a six. This value also clears the PED3 bit to

assign

IRQ3 to be level triggered.

c. Interrupts are enabled by issuing an ei instruction.

4. The FDM buffer must be initialized because the FPRC bit is clear. To initialize the

FDM buffer,

FCNT samples are written to the FDM through the FDIR. The code

uses a short loop to write the first

FCNT input samples to the FDIR using a move.l

instruction.

5. The FCM buffer must be initialized because the FCTL[7]:FCIM bit is set. After the

FKIR value is written to the K-constant input register, the EFCOP initializes the

FCM buffer using a coefficient update session with the original coefficients equal

to zero (so it does not matter what the values are in the FCM buffer memory

locations before the code begins).

6. Processing begins with the write of the first input data sample to the FDIR.

1 2 ... 188 189 190 191 192 193 194 195 196 197 198 ... 345 346

No comments

Motorola MSC8101 ADS User's Guide Page 193