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Select the TSA Channel Route to a TDM Timeslot
Multi-Channel Controllers (MCCs) 10-15
Figure 10-9. Serial Interface Entry Definitions for Driver Example
10.4.2 Set up Clocks, Baud Rate Generators (BRG), and Timers
The TDMB clocks (L1RCLKB, L1TCLKB) are always driven from an external source. In
our example, they are configured to be driven from the CLK[15–16] pins (the CMX SI2
Clock Route Register [CMXSI2CR] is cleared to 0x0). The reference clock input to these
pins is either from the T1/E1 framer, in external PHY loopback, or from the BRG in
internal (SI or TDM) loopback. The driver implements internal loopback clock generation
via BRG5. The BRG5 output is a fraction of the CPM BRGCLK clock and is determined
by the division factors programmed in the BRG Configuration (BRGC) registers. To give
a clock rate of ~2.048 MHz from a 150 MHz CPM, BRGC5 is set to 0x00010048. The
BRG is set for normal operation, with no prescaler and a clock divider of 37. The clocks
produced by the BRGs are sent to the bank-of-clocks logic, where they are either routed to
the serial controllers or to the external pins, as in this case. The
BRG50 pin must be
externally connected to the
CLK15 pin.
To provide the synchronization signals, the following CPM timer registers require
configuration:
1. Timer Global Configuration Register (TGCR). TGCR must be configured prior to
the TMR or erratic behavior can occur. Setting TGCR1 = 0x09 enables Timer1
with normal gate mode.
2. Timer Mode Register (TMR). Next, the TMR1 register is configured with the timer
prescaler set to 1, the capture event disabled and the timer counter is reset
immediately after the reference value is reached. The input source for the timer is
TIN1 (fed by BRG5); therefore TIMR1 is set to 0x000E.
Loop/
echo
Super
MCSEL
LST
CNT
BYT
Channel 160
Rx entry
Channel 160
Tx entry
Channel 191
Rx entry
Channel 191
Tx entry
0
1 0 1 0 0 0 0 0
0 0 01
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0 0 0
0 0 0
0 0 0
1 0 1 0 0 0 0 0
1 0 1 1 1 1 1 1
1 0 1 1 1 1 1 1
- MSC8101 USER’S GUIDE 1
- How to reach us: 2
- 1-303-675-2140 2
- 1-800-441-2447 2
- Chapter 5 7
- Chapter 11 10
- Chapter 12 10
- EOnCE/JTAG 10
- Contents 11
- MSC8101 User’s Guide xi 11
- MSC8101 User’s Guide xiii 13
- MSC8101 User’s Guide xv 15
- MSC8101 User’s Guide xvii 17
- About This Book 19
- Audience and Helpful Hints 20
- Organization 21
- Other MSC8101 Documentation 23
- Further Reading 23
- Chapter 1 25
- MSC8101 Overview 25
- 1.2 Features 26
- 1.2.2 On-Device Memories 27
- 1.2.5 System Interface Unit 27
- 1.2.6 On-Device Peripherals 28
- 1.2.7 DMA Engine 28
- 1.3 Architecture 30
- 1.3.2 SRAM 31
- 1-8 MSC8101 User’s Guide 32
- Extended Core 32
- 1.3.4 DMA Controller 33
- Offset 0123456789101112131415 37
- 0x0 Status and Control 37
- 0x2 Data Length 37
- 0x4 High-Order Buffer Pointer 37
- 0x6 Low-Order Buffer Pointer 37
- MSC8101 Reference Manual 38
- Architecture 39
- MSC8101 Overview 1-15 39
- Table 1-6. SCC Parameter RAM 40
- MSC8101 Overview 1-17 41
- 1-18 MSC8101 User’s Guide 42
- MSC8101 Overview 1-19 43
- 1-20 MSC8101 User’s Guide 44
- Centralized DSP Architecture 48
- MSC8101 Application Examples 49
- MSC8101 Overview 1-25 49
- Serial Backplane 49
- 1.5 Software Development 50
- Software Development 51
- MSC8101 Overview 1-27 51
- 1-28 MSC8101 User’s Guide 52
- Chapter 2 53
- Reset Configuration and Boot 53
- 2.1.1 Bootloader Program 54
- 2.1.2 Clocks 54
- Connected 59
- Address Bus 60
- Data Bus 60
- BTM[0–1]/EE[4–5] 63
- Host Port 64
- 2-16 MSC8101 User’s Guide 68
- 2.5 Related Reading 69
- 2-18 MSC8101 User’s Guide 70
- Chapter 3 71
- 3.2 Partitioning Memory 72
- 3.3 Allocating Memory 72
- 3.5 Related Reading 75
- 3-6 MSC8101 User’s Guide 76
- Chapter 4 77
- Memory-Mapped Devices 77
- 4.2 External Bus Basics 78
- AM29LV160D 80
- 2MB Flash 80
- 01234 0567 9EHTR8 81
- 01234 05678910 82
- Table 4-1. GPCM ORx Settings 83
- READ, WRITE, and PRECHARGE 85
- ACTIVATE command 85
- 4-10 MSC8101 User’s Guide 86
- CAS latency = 2, Last Data 86
- 4-12 MSC8101 User’s Guide 88
- Multiplex 89
- 4-14 MSC8101 User’s Guide 90
- GPL2 is programmed high in a 91
- CSx = HCS 94
- 4.6 Related Reading 95
- 4-20 MSC8101 User’s Guide 96
- System and Local Buses 97
- 5.1 PowerPC System Bus 98
- PowerPC System Bus 99
- QBus Switch 99
- 5.2 PowerPC Local Bus 100
- 5.3 Bus Interaction 101
- Figure 5-6. Bus Architecture 102
- 5.3.1 DMA Controller 104
- 5.3.2 SDMA Channels 105
- Figure 5-8. SDMA Data Paths 106
- 5.4 Related Reading 107
- 5-12 MSC8101 User’s Guide 108
- Chapter 6 109
- DMA Channels 109
- 6.1.1 Operating Modes 110
- 6.1.2 Transfer Types 111
- External 112
- 6.2 Initializing the DMA 115
- Table 6-2. DCHCRx Bits 116
- Table 6-3. DCPRAM Addressing 117
- 6-10 MSC8101 User’s Guide 118
- 6.2.6 FIFO Requests 120
- 6.2.9 Interrupts 121
- These signals are: 122
- (DMA request) 122
- (DMA acknowledge) 122
- 6-16 MSC8101 User’s Guide 124
- from the vector base 132
- 6.6 Related Reading 134
- Chapter 7 135
- PERIPH_IR 137
- 7.3.4 Routing Interrupts 140
- 0x0 TRAP 141
- 7.4.1 PIC Programming 143
- 7.4.4 PIC Macros 147
- Chapter 8 153
- Host Interface (HDI16) 153
- 8.1.1 Host-Side Model 154
- 8.1.2 DSP-Side Model 155
- 8.2.1 Normal Mode 157
- 8-6 MSC8101 User’s Guide 158
- 8.2.2 Host DMA Mode 160
- Host Interface (HDI16) 8-9 161
- HDM0 is 161
- HPCR[15]:OAD Data Valid 162
- 0 HACK pin is asserted 162
- Figure 8-3 163
- 8-12 MSC8101 User’s Guide 164
- 8.3.1 Software Polling 165
- 8.3.2 DSP Interrupts 167
- Table 8-16. PIC Interrupts 168
- Host Interface (HDI16) 8-17 169
- 8.3.3 Host Requests 170
- Host Interface (HDI16) 8-19 171
- Host Interface (HDI16) 8-21 173
- 8-22 MSC8101 User’s Guide 174
- Host Interface (HDI16) 8-23 175
- 8.5 Related Reading 176
- Chapter 9 177
- 9-2 MSC8101 User’s Guide 178
- 9-4 MSC8101 User’s Guide 180
- 9.2.2 Complex Mode 181
- 9.2.4 Magnitude Mode 182
- 9-8 MSC8101 User’s Guide 184
- 9.4.1 Rounding 185
- 9-10 MSC8101 User’s Guide 186
- 9.5.1 Polling 187
- 9.5.2 Interrupts 188
- 9.5.3 DMA 189
- 9.6 Programming Examples 190
- FCNT/2 complex 191
- 9-20 MSC8101 User’s Guide 196
- FDOR_ADDR, is written to the 197
- NSAMP/4 data samples are 197
- Programming Examples 199
- 9.7 Related Reading 201
- 9-26 MSC8101 User’s Guide 202
- Chapter 10 203
- 10.1.2 Driver Memory Map 206
- 10.1.3 Memory Usage 207
- × 64 Kbps slots 208
- 10-8 MSC8101 User’s Guide 210
- Figure 10-7. Loopback Modes 211
- × 8), thus creating a 211
- 10.3 Configure the Channels 212
- 0x3800 is used 213
- 10-14 MSC8101 User’s Guide 216
- CLK15 pin 217
- BRG50 pin must be 217
- 10.6 Related Reading 218
- 11.2 Setting the Clock 221
- 11-4 MSC8101 User’s Guide 222
- Operating the SPI as a Master 223
- Figure 11-3. SPI as a Master 224
- 11-8 MSC8101 User’s Guide 226
- Figure 11-4. SPI as Slave 227
- Operating the SPI as a Slave 229
- 11.7 Related Reading 231
- 11-14 MSC8101 User’s Guide 232
- 12-2 MSC8101 User’s Guide 234
- 12.1.1 Instructions 235
- 12-4 MSC8101 User’s Guide 236
- 12.1.3 Registers 237
- 12-6 MSC8101 User’s Guide 238
- EOnCE/JTAG Basics 239
- EOnCE/JTAG 12-7 239
- 12-8 MSC8101 User’s Guide 240
- EOnCE/JTAG 12-9 241
- 12.1.3.1 CORE_CMD Example 1 242
- 12.1.3.2 CORE_CMD Example 2 242
- 12.1.3.3 CORE_CMD Example 3 242
- EOnCE/JTAG 12-11 243
- 12-12 MSC8101 User’s Guide 244
- EOnCE/JTAG 12-13 245
- 12-14 MSC8101 User’s Guide 246
- Figure 12-8. Writing to ERCV 247
- 12.7 Downloading Software 248
- Downloading Software 249
- EOnCE/JTAG 12-17 249
- 12-18 MSC8101 User’s Guide 250
- EOnCE/JTAG 12-19 251
- 12.10 Counting Core Cycles 252
- Counting Core Cycles 253
- EOnCE/JTAG 12-21 253
- 12.11 Related Reading 254
- Appendix A 255
- Programming Reference 255
- A-2 MSC8101 User’s Guide 256
- MSC8101 User’s Guide A-3 257
- A-4 MSC8101 User’s Guide 258
- MSC8101 User’s Guide A-5 259
- A-6 MSC8101 User’s Guide 260
- A.2 Programming Sheets 261
- SYSTEM INTERFACE UNIT 262
- Address: 0x10240 263
- Reset: 0 263
- Read/Write 263
- Address: 0x10220 267
- MEMORY CONTROLLER 268
- BR[0–7, 10, 11] 268
- OR[0–7, 10, 11] 269
- MAMR, MBMR, MCMR 272
- INTERRUPT SCHEME 275
- SICR/SICR_EXT 278
- SIEXR/SIEXR_EXT 278
- DIRECT MEMORY ACCESS 279
- DCHCR[0–15] 281
- ENHANCED FILTER 283
- COPROCESSOR 283
- Address: 0x0C80 284
- Host Control Register 286
- Address: 0x0000 286
- Hardware Reset: 0 286
- HCR (HICR=1) 287
- HOST INTERFACE 287
- Host Port Control Register 288
- Address: 0x0020 288
- ICR (DMA=0, DMA=1, HICR=0) 289
- ICR (DMA=0, DMA=1, HICR=1) 290
- Appendix B 291
- Glossary 291
- Glossary Appendix B-3 293
- Debug mode 295
- DSP MIPs 296
- Glossary Appendix B-7 297
- FC-PBGA 298
- Glossary Appendix B-9 299
- Glossary Appendix B-11 301
- Glossary Appendix B-13 303
- TXD, RXD, and SMSYN 303
- Glossary Appendix B-15 305
- Glossary Appendix B-17 307
- Appendix C 309
- Bootloader Program 309
- 0x80 310
- 0 310
- 0x100 310
- 0x180 310
- long instead of bytes 313
- C-16 MSC8101 User’s Guide 324
- Appendix D 325
- Acronyms and Abbreviations 325
- D-2 MSC8101 User’s Guide 326
- Flip Chip-Plastic Ball Grid 327
- Array package 327
- D-4 MSC8101 User’s Guide 328
- MSC8101 User’s Guide D-5 329
- D-6 MSC8101 User’s Guide 330
- MSC8101 User’s Guide D-7 331
- D-8 MSC8101 User’s Guide 332
- MSC8101 User’s Guide D-9 333
- D-10 MSC8101 User’s Guide 334
- Numerics 335
- , 1-4, 1-22, 4-2, 5-3 339
- SET command 4-7 342
- -ALL-BANKS command 4-7 344
- , 10-1, 10-8 346
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