Motorola MSC8101 ADS User's Guide download pdf (Page 86)

4-10 MSC8101 User’s Guide

Connecting External Memories and Memory-Mapped Devices

Table 4-2 summarizes the control settings of the MSC8101 SDRAM controller.

4.4.3 Single-Bus Mode SDRAM Timing Control Settings

The timing parameters for accessing an SDRAM device must be carefully selected based

on a timing analysis between the MSC8101 and the SDRAM that includes any external

glue logic required. For Single-Master MSC8101 Bus mode, you can connect the devices

directly and verify one set of AC timing characteristics against another. Several

programmable timing parameters are available within the MSC8101 SDRAM controller.

Typically, these parameters vary according to the associated timing of the SDRAM. When

an access misses an 8 ns K4S643232C SDRAM page, the read access profile is 5-1-1-1.

The write access profile is 3-1-1-1 clocks. The Single-Master MSC8101 Bus mode read

access is shown in Figure 4-7 and the write access in Figure 4-8, respectively.

For the read access, the SDRAM controller assumptions are

CAS latency = 2, Last Data

Out to Precharge = –1, and Precharge to Activate = 2 clocks. The underlying assumption

here is that the 30 pF output timing is used in Single-Master MSC8101 Bus mode to meet

the SDRAM address set-up time. Also, an 8 ns (125 MHz) SDRAM is used for aggressive

set-up and hold times to meet the MSC8101 specifications. This particular SDRAM at 125

MHz also has the advantage that a

CAS latency of 2 is possible compared to a CAS latency

of 3 with a 100 MHz SDRAM.

Table 4-2. SDRAM Control Settings

PSDMR[PBI] = 0b1 Page-based interleaving is used.

PSDMR[SDAM] = 0b010 Addresses A[5–21] are multiplexed on the physical address pins A[15–31].

PSDMR[BSMA] = 0b111 Addresses A[19–21] are output on BNKSEL[0–2]

PSDMR[SDA10] = 0b001 Address A9 connects to SDA10

OR[SDAM] = 0xFF8

OR[LSDAM] = 0b00000 8 MB size of SDRAM

OR[BPD] = 0b01 4 banks per device

OR[ROWST] = 0b0110 A9 is Row Start Address line

OR[NUMR] = 0b010 11 row address lines

OR[PMSEL] = 0 Page-based interleaving only

OR[IBID] = 0 Page-based interleaving only

NOTE: These settings are for a 32-bit Samsung K4S643232C SDRAM memory. For other memory types and

64-bit wide options, these values differ.

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Motorola MSC8101 ADS User's Guide Page 86