Motorola MSC8101 ADS User's Guide download pdf (Page 104)

5-8 MSC8101 User’s Guide

Balancing Between the PowerPC System and Local Buses

5.3.1 DMA Controller

The multi-channel DMA controller connects to both the PowerPC system bus and the

PowerPC local bus. Data from the extended core transfers from the PowerPC local bus to

the PowerPC system bus and vice versa.

5.3.1.1 Selecting a Bus

The DMA Channel Configuration Register DCHCRx[PPC] bit selects the PowerPC bus

associated with the channel. Clearing this bit assigns the channel to the PowerPC local

bus, and setting this bit assigns the channel to the PowerPC system bus. For example,

when data is transferred from an external peripheral on the PowerPC system bus to the

DMA FIFO, the DCHCRx[PPC] bit is set to select the PowerPC system bus. When data is

transferred from an internal peripheral such as the EFCOP, which is located on the

PowerPC local bus to internal SRAM, the DCHCRx[PPC] is cleared to select the

PowerPC local bus.

5.3.1.2 DMA FIFO

The DMA uses a FIFO for its data transfers. Therefore, one bus can transfer its data to the

DMA FIFO and be free of the data transaction instead of waiting with the data until the

other bus is free. For example, in a transfer from the EFCOP data output register to

memory on the PowerPC system bus, the data is transferred on the PowerPC local bus to

the DMA FIFO, and the PowerPC local bus is released. Subsequently, the DMA arbitrates

for access to the PowerPC system bus. When access is granted, the DMA transfers the data

from the DMA FIFO to external memory, completing the transfer. The PowerPC local bus

does not have to wait for access to the PowerPC system bus before it can execute a second

transfer, which could be from the CPM to internal SRAM, for example.

5.3.1.3 Chained Buffers

A chained buffer is a type of buffer that jumps to the address of the next buffer when its

size reaches zero. If the buffers use different buses—for example, one buffer maps to the

PowerPC system bus while the other maps to the PowerPC local bus—the flush option

should be used to prevent out-of-sequence transactions from crossing the buses. When

data in the FIFO is flushed, data is transferred to the destination. The Buffer Attributes

BD_ATTR[FLS] bit configures the behavior of the DMA FIFO when BD_SIZE reaches

zero. Clearing this bit does not flush the FIFO, and setting this bit flushes the FIFO.

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Motorola MSC8101 ADS User's Guide Page 104