Programmable Interrupt Controller (PIC)
Interrupts and Interrupt Priorities 7-3
■ Support for software acknowledgment of all edge-triggered IRQ and NMI.
■ Visibility to all pending IRQ.
■ Support for nine priority levels:
— Interrupt disabled (level 0).
— Interrupt enabled (levels 1-7, where 7 is the highest priority).
— NMI level (8 inputs only).
■ Support for location-dependent priority for equi-level IRQ and NMI.
■ Ability to work with slow peripherals in edge-triggered/level-triggered modes.
Figure 7-2. PIC Block Diagram
QBus
64-bit
RIPL[0–2]
NMIR
IRQ
VAB[0–5]
VAB_EN
IR0
IR23
NMI_7
PERIPH_IR
NMI_IR
DATA[0–15]
NMI_0
ELIRA REGISTER
Pending Register
Priority and
Location Filter
VAB
GEN
REMAIN_INT
IPR
VAB
Control
Control
ELIRB REGISTER
ELIRC REGISTER
ELIRD REGISTER
ELIRE REGISTER
ELIRF REGISTER
IPRA REGISTER
IPRB REGISTER
NMI
16-bit
Interface Unit
SC140 Core
QBus
Interface
NOTE: Bolded lines are bus lines; the thinner lines are control and data lines.
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