6-10 MSC8101 User’s Guide
DMA Channels
Each DMA channel uses buffer descriptors in the DCPRAM to point to a buffer and
characterize it. The buffer descriptor contains four distinct parameters: address
(BD_ADDRn), size (BD_SIZEn), base size (BD_BSIZEn), and attributes (BD_ATTRn).
Each DMA channel selects the buffer descriptor by setting DCHCRx[10–15]:BDPTR.
Therefore, DMA channel 15 and DMA channel 3 can both use the same buffer descriptor
if the parameters for both transfers are the same, but these channels can be requested by
different sources. Table 6-4 describes the four types of buffer descriptor parameters for
DMA data transactions.
2 0xF0010820 BD_ADDR2 0xF0010824 BD_SIZE2 0xF0010828 BD_ATTR2 0xF001082C BD_BSIZE2
3 0xF0010830 BD_ADDR3 0xF0010834 BD_SIZE3 0xF0010838 BD_ATTR3 0xF001083C BD_BSIZE3
4 0xF0010840 BD_ADDR4 0xF0010844 BD_SIZE4 0xF0010848 BD_ATTR4 0xF001084C BD_BSIZE4
5 0xF0010850 BD_ADDR5 0xF0010854 BD_SIZE5 0xF0010858 BD_ATTR5 0xF001085C BD_BSIZE5
6 0xF0010860 BD_ADDR6 0xF0010864 BD_SIZE6 0xF0010868 BD_ATTR6 0xF001086C BD_BSIZE6
7 0xF0010870 BD_ADDR7 0xF0010874 BD_SIZE7 0xF0010878 BD_ATTR7 0xF001087C BD_BSIZE7
8 0xF0010880 BD_ADDR8 0xF0010884 BD_SIZE8 0xF0010888 BD_ATTR8 0xF001088C BD_BSIZE8
9 0xF0010890 BD_ADDR9 0xF0010894 BD_SIZE9 0xF0010898 BD_ATTR9 0xF001089C BD_BSIZE9
10 0xF00108A0 BD_ADDR10 0xF00108A4 BD_SIZE10 0xF00108A8 BD_ATTR10 0xF00108AC BD_BSIZE10
11 0xF00108B0 BD_ADDR11 0xF00108B4 BD_SIZE11 0xF00108B8 BD_ATTR11 0xF00108BC BD_BSIZE11
12 0xF00108C0 BD_ADDR12 0xF00108C4 BD_SIZE12 0xF00108C8 BD_ATTR12 0xF00108CC BD_BSIZE12
13 0xF00108D0 BD_ADDR13 0xF00108D4 BD_SIZE13 0xF00108D8 BD_ATTR13 0xF00108DC BD_BSIZE13
14 0xF00108E0 BD_ADDR14 0xF00108E4 BD_SIZE14 0xF00108E8 BD_ATTR14 0xF00108EC BD_BSIZE14
15 0xF00108F0 BD_ADDR15 0xF00108F4 BD_SIZE15 0xF00108F8 BD_ATTR15 0xF00108FC BD_BSIZE15
... ... ... ... ... ... ... ... ...
64 0xF0010BF0 BD_ADDR15 0xF0010BF4 BD_SIZE15 0xF0010BF8 BD_ATTR15 0xF0010BFC BD_BSIZE15
Table 6-4. Buffer Descriptor Parameters
Parameter Description
BD_ADDR Address
Describes either the source or destination of the DMA data transfer. For a read cycle, BD_ADDR
describes the source address of the DMA transfer. For a write cycle, BD_ADDR describes the
destination address of the transfer. The BD_ADDR for a flyby request must be programmed to the
memory address.
Table 6-3. DCPRAM Addressing (Continued)
DMA
Channel
Memory Map
Address
*
Channel
Buffer
Address
Memory
Map
Address
*
Channel
Transfer
Size
Memory
Map
Address
*
Channel
Attributes
Memory
Map
Address
*
Channel
Transfer
Base Size
* These addresses assume that the PowerPC Bus memory map is based at 0xF0000000. This is the default value for the
Internal Memory Map Register (IMMR) at reset.
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