Motorola MSC8101 ADS User's Guide Page 77

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MSC8101 User’s Guide 4-1
Chapter 4
Connecting External Memories and
Memory-Mapped Devices
This chapter illustrates several memory interconnection options for the MSC8101 bus and
memory controller. It outlines the hardware connections and memory register settings for
the MSC8101 when the PowerPC system bus connects to EPROM, Flash memory,
Synchronous DRAM (SDRAM), or an MSC8101 HDI16 slave.
4.1 Memory Controller Basics
The MSC8101 has three integrated memory controllers tailored to suit a variety of bus
control profiles. This chapter discusses all of these memory controllers and illustrates
them with examples:
General-purpose chip-select machine (GPCM). A baseline controller for simple
non-multiplexed interfaces such as EPROM, Flash memory, and SRAM. A
GPCM-derived chip select interfaces simple, non-bursting devices over a selection
of port sizes (8-, 16-, 32- and 64-bit) and a wide range of speed grades. To illustrate
its use, the timing of a Flash EPROM interface example is discussed.
Dedicated SDRAM controller. Gluelessly connects to a variety of
JEDEC-compatible SDRAMs of varying size and number of banks. The SDRAM
controller generates the row address strobe (
RAS), column address strobe (CAS), chip
select (
CS), and control signal combinations. The programmable address
multiplexing and timing characteristics enable you to control the size of the
SDRAM, row to column address latch timing, page-mode burst operation, and
bank interleaving. To illustrate SDRAM controller operation, this chapter discusses
the interface to a 100-125 MHz SDRAM on the 100 MHz Bus.
User-programmable machine (UPM). A flexible alternative controller by which
users can define a fully programmable bus cycle profile for a range of such
standard or proprietary interfaces as SRAM, EDO DRAM, and ASICs. The UPM
offers much more flexibility in timing to target a broader range of system devices
than the GPCM. Through the UPM-controlled interface, software can define the
chip selects and control strobes on each bus clock to a one quarter of one clock
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