Motorola MSC8101 ADS User's Guide download pdf (Page 296)

Appendix B-6 MSC8101 User’s Guide

Glossary

DMA

Direct memory access. A fast method of moving data from a storage

device to RAM, which speeds up processing. The MSC8101

multi-channel DMA controller supports up to 16 time-multiplexed

channels and buffer alignment by hardware. The DMA controller

connects to both the PowerPC system bus and the local PowerPC bus

and can function as a bridge between both buses. The MSC8101

DMA controller supports flyby transactions to either bus. The DMA

controller enables hot swap between channels, by time-multiplexed

channels with no cost in clock cycles. Sixteen priority levels support

synchronous and asynchronous transfers on the bus and give a varying

bus bandwidth per channel. The DMA controller can service multiple

requestors. A requestor can be any one of four external peripherals,

two internal peripherals, or sixteen internal requests generated by the

DMA FIFO itself. See also flyby transfer.

DRAM

Dynamic random-access memory. Dynamic memory is solid-state

memory in which the stored information decays over a period of time.

The decay time can range from milliseconds to seconds depending on

the device and its physical environment. The memory cells must

undergo refresh operations often enough to maintain the integrity of

the stored information. The dynamic nature of the circuits for DRAM

require data to be written back after being read, hence the difference

between access time and cycle time. DRAM memory is organized as a

rectangular matrix addressed by rows and columns. Every DRAM

must have every row refreshed within a certain time window, such as

2 milliseconds, or the information in the DRAM can be lost.

DSP MIPs

At its initial clock speed of 300 MHz, the SC140 core can execute

1,200 true DSP MIPS—1.2 billion multiply-accumulate operations,

together with associated data movement functions and pointer

updates—per second. One such DSP MIPS is the equivalent of several

RISC MIPS, the performance measure used by some other DSPs. For

purposes of comparison, the SC140 core can be said to perform 3000

RISC MIPS—ten RISC operations per cycle at 300 MHz. Moreover,

the MSC8101 enhanced filter coprocessor (EFCOP) performs filtering

operations at a 70 percent usage rate—a typical average for EFCOP

utilization in DSP applications—the coprocessor provides 210 MIPS

above the SC140 core’s 1,200-MIPS performance.

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Motorola MSC8101 ADS User's Guide Page 296