Motorola MVME172 User Manual Page 347
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I
N
D
E
X
MC2 chip/VMEchip2 redundancies 1-5
MC68060
bus master support for 82596CA 3-4
indivisible cycles 1-58
indivisible RMW memory accesses 1-58
MCECC 5-1
features 5-1
functional description 5-2
internal register memory map 5-10
introduction 5-1
specifications 5-3
MCECC chip Memory Controller ASIC 1-3
MCECC internal register memory map
memory map
MCECC internal register 1-35
Memory Base Address Registers, IP2 chip
4-19
Memory Configuration Register 5-15
memory maps
BBRAM configuration area 1-41
BBRAM, TOD clock 1-40
Ethernet LAN 1-38
IP2 chip devices 4-9
IP2 chip, all devices 1-28
IP2 chip, Control and Status Registers
1-29, 4-11
local bus 1-9
local bus, 200/300-Series 1-10
local bus, 400/500-Series 1-12
local I/O devices, 200/300-Series 1-14
local I/O devices, 400/500-Series 1-18
MC2 chip 1-27
MCECC internal registers 5-10
SCSI 1-39
time-of-day clock 1-42
VMEbus 1-46
VMEchip2 GCSR 1-26, 2-104
VMEchip2 LCSR 1-22, 2-22
Z85230 SCC register 1-37
memory map of the MC2 chip registers 3-8
memory mezzanine board serial number 1-45
Memory Size Registers, IP2 chip 4-21
memory space
16-bit IP_a 4-47
32-bit IP_ab 4-48
8-bit IP_a 4-46
memory space accesses, IP 4-52
microprocessor 1-3
MIEN 2-75, 2-97, 3-12
Miscellaneous Control Register 2-99
MK48T58 memory map 1-40
MPU
local bus time-out 1-51
off-board error 1-51
parity error 1-50
Status and DMA Interrupt Count
Register 2-63
Status Register 3-46
VMEchip2 and 2-52
MPU TEA, cause unidentified 1-51
MVIP IndustryPack interfaces 1-4
MVME172
features 1-3
functional description 1-5
introduction 1-1
MVME172 Version Register 3-35
MVME712x transition boards 1-2
N
no address increment DMA transfers 2-12
non-ECC DRAM controller 3-5
non-privileged access cycles 2-34, 2-37
Non-Volatile RAM (NVRAM) 1-3
no-VMEbus option 1-5
NVRAM memory map 1-40
O
overflow counter 2-73, 2-74
overview, MVME172 1-1
P
P2 chip 1-2
parity checking 3-5
performance, MCECC 5-2
- VME Embedded Controller 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- Manual Terminology 3
- Recent Updates 4
- Place holder 6
- Contents 7
- 1 ..............2-29 8
- 2 ...............2-31 9
- 1Board Description 19
- Requirements 22
- Block Diagrams 23
- RESET switch control 26
- Memory Maps 27
- (Continued) 33
- Detailed I/O Memory Maps 39
- 1514131211109876543210 44
- ABORT Switch 45
- RESET Switch 45
- (Continued) 48
- 0Memory Maps 59
- $FFFC1FF7 Checksum 1 60
- VMEbus Memory Map 64
- Sources of Local BERR* 66
- Functional Blocks 82
- VMEbus to Local Bus Interface 87
- Tick and Watchdog Timers 92
- VMEbus Interrupter 94
- VMEbus System Controller 95
- VMEchip2 100
- LCSR Programming Model 101
- OPER R/W 107
- WAIT RMW 132
- LVFAIR LVRW 133
- RESET switch is disabled 149
- WDBFE WDS/L WDRSE 150
- 2VMEchip2 153
- ABORT switch 175
- ABORT switch is depressed 175
- GPOEN3 GPOEN2 GPOEN1 GPOEN0 175
- GPIOO3 GPIOO2 GPIOO1 GPIOO0 176
- GCSR Programming Model 179
- Programming the GCSR 181
- Bit Numbers 182
- 3MC2 Chip 189
- Functional Description 190
- BBRAM Interface 191
- 82596CA LAN Interface 191
- MC2 Chip 192
- SRAM Memory Controller 193
- Z85230 SCC Interface 194
- Tick Timers 195
- Watchdog Timer 196
- Local Bus Timer 196
- D31-D24 D23-D16 D15-D8 D7-D0 197
- Programming Model 198
- MC2 Chip ID Register 199
- MC2 Chip Revision Register 199
- General Control Register 200
- Programming the Tick Timers 203
- Tick Timer 1 Compare Register 204
- Tick Timer 1 Counter 204
- Tick Timer 2 Compare Register 204
- Tick Timer 2 Counter 205
- LSB Prescaler Count Register 205
- LANC Error Status Register 218
- SCSI Error Status Register 221
- MVME172 Version Register 223
- Tick Timer 3 Compare Register 225
- Tick Timer 3 Counter 225
- Bus Clock Register 226
- RESET Switch Control Register 230
- DRAM Control Register 233
- MPU Status Register 234
- 4IP2 Chip 237
- IP2 Chip 240
- Programmable Clock 243
- Error Reporting 243
- Interrupts 244
- Overall Memory Map 245
- Chip ID Register 253
- Chip Revision Register 253
- Vector Base Register 254
- NAME($0A) 257
- NAME($0B) 257
- NAME($0C) 258
- NAME($0D) 258
- NAME($0E) 258
- NAME($0F) 258
- Registers 259
- NAME($18) 260
- NAME($19) 260
- NAME($1A) 260
- NAME($1B) 260
- IP Clock Register 264
- IP RESET Register 266
- IPEND CHANI 270
- OPER RRRRRRRS 272
- WIDTH1 WIDTH0 273
- DMAEI DMAEO 275
- 8-Bit Memory Space 282
- 16-Bit Memory Space 283
- 32-Bit Memory Space 284
- IP_a I/O Space 285
- IP_ab I/O Space 286
- IP_a ID Space 287
- IP to Local Bus Data Routing 288
- I/O and ID Space Accesses 290
- Introduction 291
- Features 291
- Cache Coherency 293
- Error Logging 297
- Arbitration 298
- Chip Defaults 298
- Register 300
- Offset Name 300
- Register Bit Names 302
- Memory Configuration Register 305
- Dummy Register 0 306
- Dummy Register 1 307
- Base Address Register 307
- BCLK Frequency Register 310
- Data Control Register 311
- Scrub Control Register 313
- Chip Prescaler Counter 315
- STON2-STON0 316
- Error Logger Register 321
- Error Address (Bits 31-24) 322
- Error Address (Bits 23-16) 323
- Error Address Bits (15-8) 323
- Error Address Bits (7-4) 323
- Error Syndrome Register 324
- Defaults Register 1 324
- Defaults Register 2 326
- Initialization 327
- Syndrome Decode 329
- ARelated Documentation 333
- Manufacturers’ Documents 334
- Document Title and Source 335
- Publication 335
- Related Documentation 336
- BUsing Interrupts on 337
- Numerics 341
- MCECC internal register 1-35 347
- Embedded Controller 353
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