Motorola MVME172 User Manual download pdf (Page 275)

Programming Model

http://www.mcg.mot.com/literature 4-39

DMA Control Register 2

This register is loaded by the processor or by DMA when it loads the

command word from the command packet. Because this register is loaded

from the command packet in the command chaining mode, the

descriptions here will also apply to the control word in the command

packet

The registers which control IP_c and IP_d are not used on the 200/300-

Series MVME172.

TOIP This bit defines the direction in which DMAC transfers

data. When this bit is high, data is transferred to the

IndustryPack. When it is low, data is transferred from the

IndustryPack.

ENTO ENTO set to a one will enable the watchdog time-out

function for DMA cycles on the IP bus. The time-out

period is fixed at approximately 1 msec. If a time-out does

occur, the IP bus cycle is terminated and the IPTO bit is

set in the DMA Status Register. Note that the

IndustryPack interface in the IP2 chip ASIC will wait

indefinitely if the ENTO bit is cleared and a DMA cycle

on the IP bus is not acknowledged. The IP2 chip ASIC

must be reset to clear this condition. It is recommended

that ENTO be set to a one.

DMAEO When DMAEO is set, DMA drives DMAEND and asserts

it during the DMA IP cycle in which the byte count

expires. When DMAEO is cleared, DMA’s DMAEND

driver is disabled.

ADR/SIZ $FFFBC025, $3D, $55, $6D (8 bits each)

BIT 76543210

NAME INTE 0

DMAEI DMAEO

ENTO TOIP 0 0

OPER R R/W R/W R/W R/W R/W R/W R/W

RESET 0 R0 R0 R0 R0 R0 R0 R0 R

1 ... 274 275 276 ... 354

No comments

Motorola MVME172 User Manual Page 275