Motorola MVME172 User Manual Page 249
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Programming Model
http://www.mcg.mot.com/literature 4-13
4
DMAC for IndustryPack a, request 0. This register set is referred to as DMACa in the text.
$20 DMA_a
STATUS
0 DLBE 0 IPEND CHANI TBL IPTO DONE
$21 DMA_a INT
CTRL
0 0 DINT DIEN DICLR DIL2 DIL1 DIL0
$22DMA ENABLE0000000DEN
$23RESERVED00000000
$24 DMA_a CON-
TROL 1
DHALT 0 DTBL ADMA WIDTH1 WIDTH0 0 XXX
$25 DMA_a
CONTROL 2
INTE 0 DMAEI DMAEO ENTO TOIP 0 0
$26RESERVED00000000
$27RESERVED00000000
$28 DMA_a LB
ADDR
LBA31 LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24
$29 DMA_a LB
ADDR
LBA23 LBA22 LBA21 LBA20 LBA19 LBA18 LBA17 LBA16
$2A DMA_a LB
ADDR
LBA15 LBA14 LBA13 LBA12 LBA11 LBA10 LBA9 LBA8
$2B DMA_a LB
ADDR
LBA7 LBA6 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0
$2C DMA_a IP
ADDR
00000000
$2D DMA_a IP
ADDR
IPA23 IPA22 IPA21 IPA20 IPA19 IPA18 IPA17 IPA16
$2E DMA_a IP
ADDR
IPA15 IPA14 IPA13 IPA12 IPA11 IPA10 IPA9 IPA8
$2F DMA_a IP
ADDR
IPA7 IPA6 IPA5 IPA4 IPA3 IPA2 IPA1 IPA0
$30 DMA_a BYTE
CNT
00000000
$31 DMA_a BYTE
CNT
BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16
$32 DMA_a BYTE
CNT
BCNT15 BCNT14 BCNT13 BCNT12 BCNT11 BCNT10 BCNT9 BCN8
$33 DMA_a BYTE
CNT
BCNT7 BCNT6 BCNT5 BCNT4 BCNT3 BCNT2 BCNT1 BCNT0
$34 DMA_a TBL
ADDR
TA31 TA30 TA29 TA28 TA27 TA26 TA25 TA24
$35 DMA_a TBL
ADDR
TA23 TA22 TA21 TA20 TA19 TA18 TA17 TA16
$36 DMA_a TBL
ADDR
TA15 TA14 TA13 TA12 TA11 TA10 TA9 TA8
$37 DMA_a TBL
ADDR
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued)
IP2 Chip Base Address = $FFFBC000
Register
Offset
Register Name
Register Bit Names
D7 D6 D5 D4 D3 D2 D1 D0
- VME Embedded Controller 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- Manual Terminology 3
- Recent Updates 4
- Place holder 6
- Contents 7
- 1 ..............2-29 8
- 2 ...............2-31 9
- 1Board Description 19
- Requirements 22
- Block Diagrams 23
- RESET switch control 26
- Memory Maps 27
- (Continued) 33
- Detailed I/O Memory Maps 39
- 1514131211109876543210 44
- ABORT Switch 45
- RESET Switch 45
- (Continued) 48
- 0Memory Maps 59
- $FFFC1FF7 Checksum 1 60
- VMEbus Memory Map 64
- Sources of Local BERR* 66
- Functional Blocks 82
- VMEbus to Local Bus Interface 87
- Tick and Watchdog Timers 92
- VMEbus Interrupter 94
- VMEbus System Controller 95
- VMEchip2 100
- LCSR Programming Model 101
- OPER R/W 107
- WAIT RMW 132
- LVFAIR LVRW 133
- RESET switch is disabled 149
- WDBFE WDS/L WDRSE 150
- 2VMEchip2 153
- ABORT switch 175
- ABORT switch is depressed 175
- GPOEN3 GPOEN2 GPOEN1 GPOEN0 175
- GPIOO3 GPIOO2 GPIOO1 GPIOO0 176
- GCSR Programming Model 179
- Programming the GCSR 181
- Bit Numbers 182
- 3MC2 Chip 189
- Functional Description 190
- BBRAM Interface 191
- 82596CA LAN Interface 191
- MC2 Chip 192
- SRAM Memory Controller 193
- Z85230 SCC Interface 194
- Tick Timers 195
- Watchdog Timer 196
- Local Bus Timer 196
- D31-D24 D23-D16 D15-D8 D7-D0 197
- Programming Model 198
- MC2 Chip ID Register 199
- MC2 Chip Revision Register 199
- General Control Register 200
- Programming the Tick Timers 203
- Tick Timer 1 Compare Register 204
- Tick Timer 1 Counter 204
- Tick Timer 2 Compare Register 204
- Tick Timer 2 Counter 205
- LSB Prescaler Count Register 205
- LANC Error Status Register 218
- SCSI Error Status Register 221
- MVME172 Version Register 223
- Tick Timer 3 Compare Register 225
- Tick Timer 3 Counter 225
- Bus Clock Register 226
- RESET Switch Control Register 230
- DRAM Control Register 233
- MPU Status Register 234
- 4IP2 Chip 237
- IP2 Chip 240
- Programmable Clock 243
- Error Reporting 243
- Interrupts 244
- Overall Memory Map 245
- Chip ID Register 253
- Chip Revision Register 253
- Vector Base Register 254
- NAME($0A) 257
- NAME($0B) 257
- NAME($0C) 258
- NAME($0D) 258
- NAME($0E) 258
- NAME($0F) 258
- Registers 259
- NAME($18) 260
- NAME($19) 260
- NAME($1A) 260
- NAME($1B) 260
- IP Clock Register 264
- IP RESET Register 266
- IPEND CHANI 270
- OPER RRRRRRRS 272
- WIDTH1 WIDTH0 273
- DMAEI DMAEO 275
- 8-Bit Memory Space 282
- 16-Bit Memory Space 283
- 32-Bit Memory Space 284
- IP_a I/O Space 285
- IP_ab I/O Space 286
- IP_a ID Space 287
- IP to Local Bus Data Routing 288
- I/O and ID Space Accesses 290
- Introduction 291
- Features 291
- Cache Coherency 293
- Error Logging 297
- Arbitration 298
- Chip Defaults 298
- Register 300
- Offset Name 300
- Register Bit Names 302
- Memory Configuration Register 305
- Dummy Register 0 306
- Dummy Register 1 307
- Base Address Register 307
- BCLK Frequency Register 310
- Data Control Register 311
- Scrub Control Register 313
- Chip Prescaler Counter 315
- STON2-STON0 316
- Error Logger Register 321
- Error Address (Bits 31-24) 322
- Error Address (Bits 23-16) 323
- Error Address Bits (15-8) 323
- Error Address Bits (7-4) 323
- Error Syndrome Register 324
- Defaults Register 1 324
- Defaults Register 2 326
- Initialization 327
- Syndrome Decode 329
- ARelated Documentation 333
- Manufacturers’ Documents 334
- Document Title and Source 335
- Publication 335
- Related Documentation 336
- BUsing Interrupts on 337
- Numerics 341
- MCECC internal register 1-35 347
- Embedded Controller 353
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