Motorola MVME172 User Manual download pdf (Page 309)

Programming Model

http://www.mcg.mot.com/literature 5-19

Difference from MEMC040: bit = WWP (write-wrong-

parity) for MEMC040; bit = RWB (general purpose read

write bit) for MCECC.

SWAIT Setting the SWAIT control bit causes the MCECC pair to

wait for MI* to be negated before starting a DRAM cycle

in response to a local bus cycle to DRAM that does not

have snooping inhibited. Clearing the SWAIT bit causes

the MCECC pair to start a DRAM read cycle even before

MI* is negated during a snooped, local bus cycle. Note

that the MCECC pair still waits for MI* to be negated

before enabling its data onto the local data bus and

asserting TA*/TEA*. Additionally, setting the SWAIT bit

causes the MCECC pair to wait for LOCKOK to be

asserted before starting a DRAM cycle in response to a

local bus cycle to DRAM that has LOCKL asserted.

Clearing the SWAIT bit causes the MCECC pair to start a

DRAM read even before LOCKOK is asserted during a

local bus cycle that has LOCKL asserted. As with MI*,

the MCECC pair still waits for LOCKOK to be asserted

before enabling its data onto the local data bus and

asserting TA*/TEA*. SWAIT should normally be

cleared, as it can provide a slight performance gain.

Difference from MEMC040: when bit set - no difference

for snooping, when bit cleared - MEMC040 REV. 1 no

difference, MEMC040 REV. 0 - MCECC pair waits for

MI* negated in all cases of snooped writes whereas

MEMC040 REV. 0 does not wait if snooped write is a line

push Additionally, for the MEMC040, SWAIT does not

affect LOCKL, LOCKOK operation. For the MCECC,

SWAIT affects LOCKL, LOCKOK operation as

explained.

RWB5 Read/Write Bit 5 is a general purpose read/write bit.

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Motorola MVME172 User Manual Page 309