Motorola MVME172 User Manual download pdf (Page 295)

Functional Description

http://www.mcg.mot.com/literature 5-5

pair writes all 144 bits. When the local bus master requests a byte, word

(two-byte), or longword write to DRAM, the MCECC pair performs a 144-

bit wide read cycle to DRAM, merges the appropriate local bus write data

in, and writes 144 bits to DRAM.

Error Reporting

The MCECCs generate the ECC check bits for write cycles. They also

check read data from the DRAM and correct it if it contains a single bit

error. If a non-correctable error occurs within either of the MCECC 72 bits

of read data, the affected MCECC indicates it by asserting its non-

correctable error (NCE*) pin.

The following paragraphs indicate the actions taken by the MCECC pair

for different error situations.

Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)

Correct the Data that is driven to the local MC68060 bus.

Do not correct the Data in DRAM. Note that the DRAM is not corrected

until the next scrub of that address, which happens only if scrubbing is

enabled.

Terminate the cycle normally. (Assert TA to the local bus.)

Log the error if one has not already been logged.

Notify the local MPU via interrupt if so enabled.

Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)

Cannot correct the data that is driven to the local MC68060 bus.

Leave the error in DRAM. (Note that it is not corrected in DRAM during

the next scrub of that address.)

Terminate the cycle with Bus Error (assert TEA to the local bus) if so

enabled.

Log the error if one has not already been logged.

Notify the local MPU via interrupt if so enabled.

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Motorola MVME172 User Manual Page 295