Motorola MVME172 User Manual Page 306
- Page / 354
- Table of contents
- BOOKMARKS
Rated. / 5. Based on customer reviews
5-16 Computer Group Literature Center Web Site
MCECC
5
RB3 Read Bit 3 is a read only bit that is always 0.
Difference from MEMC040: bit = WPB (write-per-bit
input strap status) for MEMC040; bit = 0 for MCECC
(WPB = 0 on current versions of MVME172).
RB4 Read Bit 4 is a read only bit that is always 1.
Difference from MEMC040: bit = EXTPEN (external
parity enable input strap status) for MEMC040; bit = 1 for
MCECC (EXTPEN = 1 on current versions of
MVME172).
FSTRD FSTRD reflects the state of the FSTRD bit in the Defaults
Register 1. When 1, this bit indicates that DRAM reads
are operating at full speed. When 0, it indicates that
DRAM read accesses are slowed by one clock cycle to
accommodate slower DRAM devices.
Difference from MEMC040: NONE except that it is an
input pin on the MEMC040; while it is a register bit that
is initialized by the reset serial bit stream on the MCECC.
Dummy Register 0
Dummy Register 0 is hard-wired to all zeros. Writes to this register are
ignored; however, the MCECC always terminates the cycles properly with
TA*.
Difference from MEMC040: register = Alternate Status
for MEMC040; register = $00 for MCECC.
ADR/SIZ 1st $FFF4300C/2nd $FFF4310C (8-bits)
BIT 31 30 29 28 27 26 25 24
NAME 00000000
OPER RRRRRRRR
RESET XXXXXXXX
- VME Embedded Controller 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- Manual Terminology 3
- Recent Updates 4
- Place holder 6
- Contents 7
- 1 ..............2-29 8
- 2 ...............2-31 9
- 1Board Description 19
- Requirements 22
- Block Diagrams 23
- RESET switch control 26
- Memory Maps 27
- (Continued) 33
- Detailed I/O Memory Maps 39
- 1514131211109876543210 44
- ABORT Switch 45
- RESET Switch 45
- (Continued) 48
- 0Memory Maps 59
- $FFFC1FF7 Checksum 1 60
- VMEbus Memory Map 64
- Sources of Local BERR* 66
- Functional Blocks 82
- VMEbus to Local Bus Interface 87
- Tick and Watchdog Timers 92
- VMEbus Interrupter 94
- VMEbus System Controller 95
- VMEchip2 100
- LCSR Programming Model 101
- OPER R/W 107
- WAIT RMW 132
- LVFAIR LVRW 133
- RESET switch is disabled 149
- WDBFE WDS/L WDRSE 150
- 2VMEchip2 153
- ABORT switch 175
- ABORT switch is depressed 175
- GPOEN3 GPOEN2 GPOEN1 GPOEN0 175
- GPIOO3 GPIOO2 GPIOO1 GPIOO0 176
- GCSR Programming Model 179
- Programming the GCSR 181
- Bit Numbers 182
- 3MC2 Chip 189
- Functional Description 190
- BBRAM Interface 191
- 82596CA LAN Interface 191
- MC2 Chip 192
- SRAM Memory Controller 193
- Z85230 SCC Interface 194
- Tick Timers 195
- Watchdog Timer 196
- Local Bus Timer 196
- D31-D24 D23-D16 D15-D8 D7-D0 197
- Programming Model 198
- MC2 Chip ID Register 199
- MC2 Chip Revision Register 199
- General Control Register 200
- Programming the Tick Timers 203
- Tick Timer 1 Compare Register 204
- Tick Timer 1 Counter 204
- Tick Timer 2 Compare Register 204
- Tick Timer 2 Counter 205
- LSB Prescaler Count Register 205
- LANC Error Status Register 218
- SCSI Error Status Register 221
- MVME172 Version Register 223
- Tick Timer 3 Compare Register 225
- Tick Timer 3 Counter 225
- Bus Clock Register 226
- RESET Switch Control Register 230
- DRAM Control Register 233
- MPU Status Register 234
- 4IP2 Chip 237
- IP2 Chip 240
- Programmable Clock 243
- Error Reporting 243
- Interrupts 244
- Overall Memory Map 245
- Chip ID Register 253
- Chip Revision Register 253
- Vector Base Register 254
- NAME($0A) 257
- NAME($0B) 257
- NAME($0C) 258
- NAME($0D) 258
- NAME($0E) 258
- NAME($0F) 258
- Registers 259
- NAME($18) 260
- NAME($19) 260
- NAME($1A) 260
- NAME($1B) 260
- IP Clock Register 264
- IP RESET Register 266
- IPEND CHANI 270
- OPER RRRRRRRS 272
- WIDTH1 WIDTH0 273
- DMAEI DMAEO 275
- 8-Bit Memory Space 282
- 16-Bit Memory Space 283
- 32-Bit Memory Space 284
- IP_a I/O Space 285
- IP_ab I/O Space 286
- IP_a ID Space 287
- IP to Local Bus Data Routing 288
- I/O and ID Space Accesses 290
- Introduction 291
- Features 291
- Cache Coherency 293
- Error Logging 297
- Arbitration 298
- Chip Defaults 298
- Register 300
- Offset Name 300
- Register Bit Names 302
- Memory Configuration Register 305
- Dummy Register 0 306
- Dummy Register 1 307
- Base Address Register 307
- BCLK Frequency Register 310
- Data Control Register 311
- Scrub Control Register 313
- Chip Prescaler Counter 315
- STON2-STON0 316
- Error Logger Register 321
- Error Address (Bits 31-24) 322
- Error Address (Bits 23-16) 323
- Error Address Bits (15-8) 323
- Error Address Bits (7-4) 323
- Error Syndrome Register 324
- Defaults Register 1 324
- Defaults Register 2 326
- Initialization 327
- Syndrome Decode 329
- ARelated Documentation 333
- Manufacturers’ Documents 334
- Document Title and Source 335
- Publication 335
- Related Documentation 336
- BUsing Interrupts on 337
- Numerics 341
- MCECC internal register 1-35 347
- Embedded Controller 353
Related products and manuals for Hardware Motorola MVME172
Hardware Motorola MPC8260 User Manual
(100 pages)
(100 pages)
Hardware Motorola SBG940 User Manual
(141 pages)
(141 pages)
Hardware Motorola SB4100 User Manual
(27 pages)
(27 pages)
Hardware Motorola M68EZ328ADS User Manual
(65 pages)
(65 pages)
Hardware Motorola BR700 User Manual
(78 pages)
(78 pages)
Hardware Motorola WR850 User Manual
(97 pages)
(97 pages)
Hardware Motorola WSM6300 User Manual
(22 pages)
(22 pages)
Hardware Motorola SB4000 User Manual
(2 pages)
(2 pages)
Hardware Motorola HC12 User Manual
(2 pages)
(2 pages)
Hardware Motorola WPS870G User Manual
(115 pages)
(115 pages)
Hardware Motorola SB5100 Series User Manual
(72 pages)
(72 pages)
Hardware Motorola WNS25 User Manual
(2 pages)
(2 pages)
© 2020, manymanuals.com. All rights reserved. | 0.134 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals