Motorola MVME172 User Manual Page 343
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DMA continued
Interrupt Control Register, IP2 chip 4-35
Local Bus Address Counter, IP2 chip
4-40
Status Register, IP2 chip 4-34
Table Address Counter, IP2 chip 4-42
transfers 2-12
DMAC
byte counter 2-61
command packets 2-53
Control Register 1 (bits 0-7) 2-56
Control Register 2 (bits 0-7) 2-59
Control Register 2 (bits 8-15) 2-57
interrupter 2-19
local bus address counter 2-60
LTO error 1-53
off-board error 1-53
parity error 1-52
registers 2-53
Status Register 2-64
TEA, cause unidentified 1-54
VMEbus address counter 2-60
VMEbus error 1-52
VMEbus requester 2-13
documentation A-1
double bit error (cycle type = burst read or
non-burst read) 5-5
double bit error (cycle type = non-burst write)
5-6
double bit error (cycle type = scrub) 5-7
DRAM 1-3
DRAM
and SRAM Memory Controller
Registers 3-25
Control Register 3-45, 5-18
memory controller, MC2 chip 3-5
Parity Error Interrupt Control Register
3-22
performance 3-6
size control bit encoding 3-27, 3-28
Space Base Address Register 3-25
Space Size Register 3-26
DRAM/SRAM Options Register 3-27
DTACK 2-9
Dummy Register 0 5-16
Dummy Register 1 5-17
DWB pin 2-8
E
ECC 5-4
edge-sensitive interrupters 2-18
edge-sensitive interrupts 2-75
ending address register 2-27, 2-38
EPROM socket 1-3
EPROM/Flash interface 3-2
EPROM/Flash sizing
200/300-Series 1-11
400/500-Series 1-13
errata sheets, chip 1-21
Error Address (Bits 15-8) 5-33
Error Address (Bits 23-16) 5-33
Error Address (Bits 31-24) 5-32
Error Address (Bits 7-4) 5-33
error conditions 1-50
Error Logger Register 5-31
error logging, ECC 5-7
error reporting 5-5
as a local bus master 4-7
as a local bus slave 4-7
IndustryPack 4-8
IP2 chip 4-7
error sources, local 1-48
Error Syndrome Register 5-34
Ethernet address 1-44
Ethernet LAN memory map 1-38
Ethernet transceiver interface 1-3
examples
generating tick timer periodic interrupt
B-1
IP 16-bit memory space 4-47
IP 32-bit I/O space 4-50
IP 32-bit memory space 4-48
IP 8-bit memory space 4-46
IP I/O space 4-49
- VME Embedded Controller 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- Manual Terminology 3
- Recent Updates 4
- Place holder 6
- Contents 7
- 1 ..............2-29 8
- 2 ...............2-31 9
- 1Board Description 19
- Requirements 22
- Block Diagrams 23
- RESET switch control 26
- Memory Maps 27
- (Continued) 33
- Detailed I/O Memory Maps 39
- 1514131211109876543210 44
- ABORT Switch 45
- RESET Switch 45
- (Continued) 48
- 0Memory Maps 59
- $FFFC1FF7 Checksum 1 60
- VMEbus Memory Map 64
- Sources of Local BERR* 66
- Functional Blocks 82
- VMEbus to Local Bus Interface 87
- Tick and Watchdog Timers 92
- VMEbus Interrupter 94
- VMEbus System Controller 95
- VMEchip2 100
- LCSR Programming Model 101
- OPER R/W 107
- WAIT RMW 132
- LVFAIR LVRW 133
- RESET switch is disabled 149
- WDBFE WDS/L WDRSE 150
- 2VMEchip2 153
- ABORT switch 175
- ABORT switch is depressed 175
- GPOEN3 GPOEN2 GPOEN1 GPOEN0 175
- GPIOO3 GPIOO2 GPIOO1 GPIOO0 176
- GCSR Programming Model 179
- Programming the GCSR 181
- Bit Numbers 182
- 3MC2 Chip 189
- Functional Description 190
- BBRAM Interface 191
- 82596CA LAN Interface 191
- MC2 Chip 192
- SRAM Memory Controller 193
- Z85230 SCC Interface 194
- Tick Timers 195
- Watchdog Timer 196
- Local Bus Timer 196
- D31-D24 D23-D16 D15-D8 D7-D0 197
- Programming Model 198
- MC2 Chip ID Register 199
- MC2 Chip Revision Register 199
- General Control Register 200
- Programming the Tick Timers 203
- Tick Timer 1 Compare Register 204
- Tick Timer 1 Counter 204
- Tick Timer 2 Compare Register 204
- Tick Timer 2 Counter 205
- LSB Prescaler Count Register 205
- LANC Error Status Register 218
- SCSI Error Status Register 221
- MVME172 Version Register 223
- Tick Timer 3 Compare Register 225
- Tick Timer 3 Counter 225
- Bus Clock Register 226
- RESET Switch Control Register 230
- DRAM Control Register 233
- MPU Status Register 234
- 4IP2 Chip 237
- IP2 Chip 240
- Programmable Clock 243
- Error Reporting 243
- Interrupts 244
- Overall Memory Map 245
- Chip ID Register 253
- Chip Revision Register 253
- Vector Base Register 254
- NAME($0A) 257
- NAME($0B) 257
- NAME($0C) 258
- NAME($0D) 258
- NAME($0E) 258
- NAME($0F) 258
- Registers 259
- NAME($18) 260
- NAME($19) 260
- NAME($1A) 260
- NAME($1B) 260
- IP Clock Register 264
- IP RESET Register 266
- IPEND CHANI 270
- OPER RRRRRRRS 272
- WIDTH1 WIDTH0 273
- DMAEI DMAEO 275
- 8-Bit Memory Space 282
- 16-Bit Memory Space 283
- 32-Bit Memory Space 284
- IP_a I/O Space 285
- IP_ab I/O Space 286
- IP_a ID Space 287
- IP to Local Bus Data Routing 288
- I/O and ID Space Accesses 290
- Introduction 291
- Features 291
- Cache Coherency 293
- Error Logging 297
- Arbitration 298
- Chip Defaults 298
- Register 300
- Offset Name 300
- Register Bit Names 302
- Memory Configuration Register 305
- Dummy Register 0 306
- Dummy Register 1 307
- Base Address Register 307
- BCLK Frequency Register 310
- Data Control Register 311
- Scrub Control Register 313
- Chip Prescaler Counter 315
- STON2-STON0 316
- Error Logger Register 321
- Error Address (Bits 31-24) 322
- Error Address (Bits 23-16) 323
- Error Address Bits (15-8) 323
- Error Address Bits (7-4) 323
- Error Syndrome Register 324
- Defaults Register 1 324
- Defaults Register 2 326
- Initialization 327
- Syndrome Decode 329
- ARelated Documentation 333
- Manufacturers’ Documents 334
- Document Title and Source 335
- Publication 335
- Related Documentation 336
- BUsing Interrupts on 337
- Numerics 341
- MCECC internal register 1-35 347
- Embedded Controller 353
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