Motorola MVME172 User Manual Page 12

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xii
Local Bus Timer................................................................................................. 3-8
Memory Map of the MC2 Chip Registers................................................................. 3-8
Programming Model................................................................................................ 3-10
MC2 Chip ID Register ..................................................................................... 3-11
MC2 Chip Revision Register ........................................................................... 3-11
General Control Register .................................................................................3-12
Interrupt Vector Base Register ......................................................................... 3-13
Programming the Tick Timers..........................................................................3-15
Tick Timer 1 and 2 Compare and Counter Registers................................ 3-15
LSB Prescaler Count Register...................................................................3-17
Prescaler Clock Adjust Register................................................................3-18
Tick Timer 1 and 2 Control Registers....................................................... 3-18
Tick Timer Interrupt Control Registers.....................................................3-20
DRAM Parity Error Interrupt Control Register ...............................................3-22
SCC Interrupt Control Register........................................................................3-23
Tick Timer 3 and 4 Control Registers ..............................................................3-24
DRAM and SRAM Memory Controller Registers........................................... 3-25
DRAM Space Base Address Register.......................................................3-25
SRAM Space Base Address Register........................................................ 3-26
DRAM Space Size Register ......................................................................3-26
DRAM/SRAM Options Register ..............................................................3-27
SRAM Space Size Register.......................................................................3-29
LANC Error Status Register.............................................................................3-30
82596CA LANC Interrupt Control Register.................................................... 3-31
LANC Bus Error Interrupt Control Register.................................................... 3-32
SCSI Error Status Register...............................................................................3-33
General Purpose Inputs Register ......................................................................3-33
MVME172 Version Register............................................................................ 3-35
SCSI Interrupt Control Register.......................................................................3-36
Tick Timer 3 and 4 Compare and Counter Registers .......................................3-37
Bus Clock Register........................................................................................... 3-38
PROM Access Time Control Register ............................................................. 3-39
Flash Access Time Control Register ................................................................3-40
ABORT Switch Interrupt Control Register...................................................... 3-41
RESET Switch Control Register......................................................................3-42
Watchdog Timer Control Register.................................................................... 3-43
Access and Watchdog Time Base Select Register............................................3-44
DRAM Control Register ..................................................................................3-45
MPU Status Register ........................................................................................ 3-46
32-bit Prescaler Count Register........................................................................3-48
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