Motorola MVME172 User Manual Page 16
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- Table of contents
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FIGURES
Figure 1-1. 200/300-Series MVME172 Block Diagram ...........................................1-6
Figure 1-2. 400/500-Series MVME172 Block Diagram ........................................... 1-7
Figure 2-1. VMEchip2 Block Diagram..................................................................... 2-5
TABLES
Table 1-1. MVME172 Features Summary.................................................................1-3
Table 1-2. Redundant Functions in the VMEchip2 and MC2 Chip ......................... 1-8
Table 1-3. 200/300-Series MVME172 Local Bus Memory Map............................ 1-10
Table 1-4. 400/500-Series MVME172 Local Bus Memory Map............................ 1-12
Table 1-5. 200/300-Series MVME172 Local I/O Devices Memory Map...............1-14
Table 1-6. 400/500-Series MVME172 Local I/O Devices Memory Map...............1-18
Table 1-7. VMEchip2 Memory Map (Sheet 1 of 3) ................................................1-22
Table 1-8. MC2 Chip Register Map ........................................................................ 1-27
Table 1-9. IP2 Chip Overall Memory Map..............................................................1-28
Table 1-10. IP2 Chip Memory Map - Control and Status Registers ....................... 1-29
Table 1-11. MCECC Internal Register Memory Map ............................................1-35
Table 1-12. Z85230 SCC Register Addresses .........................................................1-37
Table 1-13. 82596CA Ethernet LAN Memory Map................................................1-38
Table 1-14. 53C710 SCSI Memory Map ...............................................................1-39
Table 1-15. MK48T58 BBRAM/TOD Clock Memory Map...................................1-40
Table 1-16. BBRAM Configuration Area Memory Map .......................................1-41
Table 1-17. TOD Clock Memory Map .................................................................... 1-42
Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2) ..................2-22
Table 2-2. DMAC Command Table Format............................................................2-53
Table 2-3. Local Bus Interrupter Summary ............................................................2-76
Table 2-4. VMEchip2 Memory Map (GCSR Summary) ...................................... 2-104
Table 3-1. DRAM Performance................................................................................. 3-6
Table 3-2. MC2 Chip Register Map ......................................................................... 3-9
Table 3-3. Interrupt Vector Base Register Encoding and Priority ...........................3-14
Table 3-4. DRAM Size Control Bit Encoding.........................................................3-27
Table 3-5. DRAM Size Control Bit Encoding.........................................................3-28
Table 3-6. SRAM Size Control Bit Encoding ......................................................... 3-28
Table 3-7. SRAM Size Control Bit Encoding ......................................................... 3-29
Table 4-1. IP2 Chip Clock Cycles .............................................................................4-6
Table 4-2. IP2 Chip Overall Memory Map ...............................................................4-9
Table 4-3. IP2 Chip Memory Map - Control and Status Registers ......................... 4-11
- VME Embedded Controller 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- Manual Terminology 3
- Recent Updates 4
- Place holder 6
- Contents 7
- 1 ..............2-29 8
- 2 ...............2-31 9
- 1Board Description 19
- Requirements 22
- Block Diagrams 23
- RESET switch control 26
- Memory Maps 27
- (Continued) 33
- Detailed I/O Memory Maps 39
- 1514131211109876543210 44
- ABORT Switch 45
- RESET Switch 45
- (Continued) 48
- 0Memory Maps 59
- $FFFC1FF7 Checksum 1 60
- VMEbus Memory Map 64
- Sources of Local BERR* 66
- Functional Blocks 82
- VMEbus to Local Bus Interface 87
- Tick and Watchdog Timers 92
- VMEbus Interrupter 94
- VMEbus System Controller 95
- VMEchip2 100
- LCSR Programming Model 101
- OPER R/W 107
- WAIT RMW 132
- LVFAIR LVRW 133
- RESET switch is disabled 149
- WDBFE WDS/L WDRSE 150
- 2VMEchip2 153
- ABORT switch 175
- ABORT switch is depressed 175
- GPOEN3 GPOEN2 GPOEN1 GPOEN0 175
- GPIOO3 GPIOO2 GPIOO1 GPIOO0 176
- GCSR Programming Model 179
- Programming the GCSR 181
- Bit Numbers 182
- 3MC2 Chip 189
- Functional Description 190
- BBRAM Interface 191
- 82596CA LAN Interface 191
- MC2 Chip 192
- SRAM Memory Controller 193
- Z85230 SCC Interface 194
- Tick Timers 195
- Watchdog Timer 196
- Local Bus Timer 196
- D31-D24 D23-D16 D15-D8 D7-D0 197
- Programming Model 198
- MC2 Chip ID Register 199
- MC2 Chip Revision Register 199
- General Control Register 200
- Programming the Tick Timers 203
- Tick Timer 1 Compare Register 204
- Tick Timer 1 Counter 204
- Tick Timer 2 Compare Register 204
- Tick Timer 2 Counter 205
- LSB Prescaler Count Register 205
- LANC Error Status Register 218
- SCSI Error Status Register 221
- MVME172 Version Register 223
- Tick Timer 3 Compare Register 225
- Tick Timer 3 Counter 225
- Bus Clock Register 226
- RESET Switch Control Register 230
- DRAM Control Register 233
- MPU Status Register 234
- 4IP2 Chip 237
- IP2 Chip 240
- Programmable Clock 243
- Error Reporting 243
- Interrupts 244
- Overall Memory Map 245
- Chip ID Register 253
- Chip Revision Register 253
- Vector Base Register 254
- NAME($0A) 257
- NAME($0B) 257
- NAME($0C) 258
- NAME($0D) 258
- NAME($0E) 258
- NAME($0F) 258
- Registers 259
- NAME($18) 260
- NAME($19) 260
- NAME($1A) 260
- NAME($1B) 260
- IP Clock Register 264
- IP RESET Register 266
- IPEND CHANI 270
- OPER RRRRRRRS 272
- WIDTH1 WIDTH0 273
- DMAEI DMAEO 275
- 8-Bit Memory Space 282
- 16-Bit Memory Space 283
- 32-Bit Memory Space 284
- IP_a I/O Space 285
- IP_ab I/O Space 286
- IP_a ID Space 287
- IP to Local Bus Data Routing 288
- I/O and ID Space Accesses 290
- Introduction 291
- Features 291
- Cache Coherency 293
- Error Logging 297
- Arbitration 298
- Chip Defaults 298
- Register 300
- Offset Name 300
- Register Bit Names 302
- Memory Configuration Register 305
- Dummy Register 0 306
- Dummy Register 1 307
- Base Address Register 307
- BCLK Frequency Register 310
- Data Control Register 311
- Scrub Control Register 313
- Chip Prescaler Counter 315
- STON2-STON0 316
- Error Logger Register 321
- Error Address (Bits 31-24) 322
- Error Address (Bits 23-16) 323
- Error Address Bits (15-8) 323
- Error Address Bits (7-4) 323
- Error Syndrome Register 324
- Defaults Register 1 324
- Defaults Register 2 326
- Initialization 327
- Syndrome Decode 329
- ARelated Documentation 333
- Manufacturers’ Documents 334
- Document Title and Source 335
- Publication 335
- Related Documentation 336
- BUsing Interrupts on 337
- Numerics 341
- MCECC internal register 1-35 347
- Embedded Controller 353
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