Motorola MVME172 User Manual download pdf (Page 142)

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VMEchip2

DMAIC The DMAC interrupt counter is incremented when an

interrupt is sent to the local bus interrupter. The value in

this counter indicates the number of commands processed

when the DMAC is operated in the command chaining

mode. If interrupt count exceeds 15, the counter rolls over.

This counter operates regardless of whether the DMAC

interrupts are enabled. This counter is cleared when the

DMAC is enabled.

DMAC Status Register

This is the DMAC status register.

DONE This bit is set when the DMAC has finished executing

commands and there were no errors or the DMAC has

finished executing command because the halt bit was set.

This bit is cleared when the DMAC is enabled.

VME When this bit is set, the DMAC received a VMEbus

BERR during a data transfer. This bit is cleared when the

DMAC is enabled.

TBL When this bit is set, the DMAC received an error on the

local bus while it was reading commands from the

command packet. Additional information is provided in

bits 3 - 6 (DLTO, DLOB, DLPE, and DLBE). This bit is

cleared when the DMAC is enabled.

DLTO When this bit is set, the DMAC received a TEA and the

status indicated a local bus time-out. This bit is cleared

when the DMAC is enabled.

ADR/SIZ $FFF40048 (8 bits of 32)

BIT 76543210

NAME MLTO DLBE DLPE DLOB DLTO TBL VME DONE

OPER RRRRRRRR

RESET 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS

1 ... 141 142 143 ... 354

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Motorola MVME172 User Manual Page 142