Motorola MVME172 User Manual download pdf (Page 327)

Programming Model

http://www.mcg.mot.com/literature 5-37

initialized by power-up, soft, or local reset to match the

NOCACHE bit in the reset serial bit stream. It should

always be left at the default value of 1.

TVECT TVECT makes bidirectional signals work while running

the vendors test vectors on this chip. It should be cleared

for normal operation. It is initialized by power-up, soft, or

local reset, to match the TVECT bit from the reset serial

bit stream.

REFDIS When REFDIS is set, refreshing is disabled. This mode

should only be used for testing, as DRAM must have

refresh to operate correctly. REFDIS is initialized by

power-up, soft, or local reset to match the REFDIS bit in

the reset serial bit stream.

XY_FLIP When XY_FLIP is set, the opposite internal set of cache

latches is selected. This bit should be used with caution

and is for test vector coverage improvement.

FRC_OPN When FRC_OPN is set, the internal DRAM read latches

are forced continuously open. This bit should be used with

caution and is for test vector coverage improvement.

Initialization

Most DRAM vendors require that the DRAMs be subjected to some

number of access cycles before the DRAMs are fully operational. The

MCECC does not perform this automatically but depends on software to

perform enough dummy accesses to DRAM to meet the requirement. The

number of required cycles is less than 10. If there are multiple blocks of

DRAM, software has to perform at least 10 accesses to each block.

The MCECC pair provides a fast zero fill capability. The sequence shown

below performs such a zero fill. It zeros all of the DRAM controlled by this

MCECC pair at the rate of 100 MB/second when the BCLK pin is

1 ... 326 327 328 ... 354

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Motorola MVME172 User Manual Page 327