Motorola MVME172 User Manual download pdf (Page 255)

Programming Model

http://www.mcg.mot.com/literature 4-19

A normal read access to the Vector Base Register yields the value $0F if

the read happens before it has been initialized. A normal read access yields

all 0’s on bits 0-2, and the value that was last written on bits 3-7, if the read

happens after the Vector Base Register was initialized.

The encoding for the interrupt sources is shown below, where IV2-IV0

refer to bits 2-0 of the vector passed during the IACK cycle:

IP_a, IP_b, IP_c, IP_d Memory Base Address Registers

The memory base address registers define the base address at which the

IP2 chip initiates memory cycles for their corresponding IndustryPacks. If

a 32-bit, double size IndustryPack is used, then the memory base address

and memory size registers for IP_a control access for double size ab and

those for IP_c control accesses for double size cd.

For each of the four sets of registers, BASE31-BASE16 are compared to

MC68060 address signals 31-16 respectively. The IP2 chip can address the

IndustryPacks only at even multiples of their size. Consequently, any bits

that are set within SIZE23-SIZE16, mask the value programmed into

BASE23-BASE16 respectively. (Masked bits always compare, regardless

of the value of the corresponding address bit.) For example, if a_SIZE16

were set, then the MC68060 address signal, A16, would not affect

comparisons for accesses to IP_a memory space. This would allow the

base address for IP_a to be programmed for one of: $00000000,

$00020000, $00040000, $00060000, etc. If both a_SIZE16 and a_SIZE17

were set, then the base address for IP_a could be programmed for one of

$00000000, $00040000, $00080000, $000C0000, etc.

IV2-0 Interrupt Source

0DMA_a

$1 DMA_b

$2 DMA_c

$3 DMA_d

$4 Programmable Clock

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Motorola MVME172 User Manual Page 255