Motorola M68CPU32BUG User Manual download pdf (Page 49)

MC68332TUT/D MOTOROLA

A. The CPU recognizes the occurrence of a valid interrupt request and begins the IACK cycle. If none

of the modules enter arbitration by asserting an IARB field value, the spurious interrupt monitor

asserts BERR internally.

B. After arbitration, the interrupt source that wins arbitration does not terminate the IACK cycle with

DSACK or AVEC. In this case, the bus monitor asserts the internal BERR signal.

C. An external device terminates the IACK cycle by asserting BERR.

An interrupt request signal remain

must

remain asserted from the time it first occurs until the end of the IACK

cycle. The most common cause of spurious interrupts is a periodic signal, such as a square wave, connect-

ed to an external interrupt request line. Other signals, such as the output of a shaft decoder, will also cause

spurious interrupts. Latch periodic or intermittent signals by means of an external circuit, and clear the latch

in the interrupt service routine.

5.2.7 Problem: The Processor Asserts HALT

and Halts

A double bus fault has occurred, and the halt monitor (previously called the double bus fault monitor) is not

enabled. A double bus fault can occur under the following conditions.

1. When bus error exception processing begins, and a second bus error is detected before the first in-

struction of the first exception handler is executed.

2. When one or more bus errors occur before the first instruction after a reset is executed.

3. When a bus error occurs while the CPU is loading information from a bus error stack frame during

execution of a return from exception (RTE) instruction.

After the double bus fault occurs, the MCU drives the HALT line low and can only be restarted by a reset.

When the HALT line is driven low internally, the double bus fault monitor will immediately cause a reset if it

is enabled. If the double bus fault monitor has been disabled by clearing the HME bit in the system protec-

tion control register (SYPCR), the MCU will remain halted indefinitely and must be reset externally.

5.2.8 Problem: A Chip-Select Generates the Wrong Number of Wait States

1. Either DSACK1 or DSACK0 has floated low. These signals should be tied high via a pull-up resistor

or be configured as I/O pins. The DSACK pins, along with other bus control signals, are configured

as I/O pins by driving DATA8 low during reset or by programming the appropriate CSPAR bits.

2. Multiple chip-selects with different wait states are responding to the same address (it does not matter

whether the chip-select pins are connected to anything). Whether or not multiple chip-selects re-

spond to the same address is determined by both the base address and the block size in the asso-

ciated chip-select base address register (CSBAR).

3. The MCU sees only base addresses that lie on a word boundary of the block size. It will interpret each

base address as an address that is on a word boundary. This will cause an incorrectly programmed

chip-select circuit to match on an unexpected address. An example of how to determine if chip-select

circuits are programmed correctly is shown below.

A. On a sheet of paper, make a table with four columns as shown in Table 8. Initialize the base ad-

dress and option registers, then look at all of the base address and option registers. Fill in the ap-

propriate cell in the table with the value in the corresponding option register and base address

base address register. Table 9 shows block size values.

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Motorola M68CPU32BUG User Manual Page 49