Motorola M68CPU32BUG User Manual download pdf (Page 39)

MC68332TUT/D MOTOROLA

4.4.2 Configuring the QSPI

The

QSPI uses a synchronous serial bus to communicate with external peripherals and other MCUs. The

QSPI serial protocol is compatible with the serial peripheral interface (SPI) on the M68HC11 and M68HC05

families of MCUs. The module also has a queue, programmable queue pointers that allow up to16 automatic

transfers, and a wrap-around mode that allows continuous transfers to and from the queue with no CPU

intervention. The queue is useful in applications such as control of an A/D convertor. Remember the fol-

lowing points when using the QSPI:

• Setting the SPE bit to enable the QSPI should be the last step in initialization.

• Data direction register DDRQS and port data register PORTQS must be initialized, even for pins that

are assigned to the QSPI in pin assignment register PQSPAR.

• Peripheral chip-select signals are asserted when a command in command RAM is executed, but the

assertion state (active high or active low) of the peripheral chip-select signal is determined by the val-

ue of the appropriate bit in PORTQS.

* This example illustrates how to initialize the QSPI in the wrap-around mode,

* with 8 data bits per transfer and active-low peripheral chip-select pins.

* Modifying the code to disable the wrap-around mode is very simple. The modifi-

* cation is explained in the comments.

SPCR1 EQU $FFFC1A

PORTQS EQU $FFFC15

PQSPAR EQU $FFFC16

DDRQS EQU $FFFC17

SPSR EQU $FFFC1F

SPCR0 EQU $FFFC18

SPCR2 EQU $FFFC1C

SPCR3 EQU $FFFC1E

SYNCR EQU $FFFA04

SYPCR EQU $FFFA21

TXDRAM EQU $FFFD20

CMDRAM EQU $FFFD40

ORG $400 ;begin program at $400, immediately after

;the exception table

INIT_SIM

MOVE.B #$7F,(SYNCR).L ;increase clock speed

CLR.B (SYPCR).L ;disable software watchdog

INIT_QSPI

ANDI.W #$7F,(SPCR1).L ;Clear the SPE bit in SPCR1 to disable

;the QSPI. Enabling the QSPI is the last

;step in the initialization sequence.

* The next command reads and clears the flags in SPSR. These flags are the

* QSPI finished flag (SPIF), the mode fault flag (MODF), and the halt

* acknowledge flag (HALTA). The SPIF bit is usually the flag of interest. It is

* set by the QSPI upon completion of a serial transfer when the address of the

* command being executed matches the ENDQP. If wrap-around mode is enabled, the

* SPIF bit is set each time the QSPI cycles through the queue. If interrupts

* are enabled, assertion of the SPIF bit causes an interrupt.

ANDI.B #$00,(SPSR).L

* The next command defines the initial states of the chip select signals in PORTQS

* (formerly called QPDR).

* The chip selects may be active high or active low. The initial state set in

* the PORTQS is the inactive state. The active state is selected in the command RAM

* In this example, the initial state of the chip

* select lines is high, and the initial state of SCK is low. This defines the

* chip selects to be active low and SCK to be active high. The SCI TXD signal

* bit is not affected.

MOVE.B #$7B,(PORTQS).L

MOVE.B #$7B,(PQSPAR).L ;Assign all pins to the QSPI. Pins can be

;assigned to the QSPI or for general

;purpose I/O on a pin by pin basis.

MOVE.B #$7E,(DDRQS).L ;Select the direction of the signal lines

;as outputs, except for MISO.

MOVE.W #$8002,(SPCR0).L ;Configure the QSPI as master, set the inactive

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Motorola M68CPU32BUG User Manual Page 39

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