Motorola M68CPU32BUG User Manual download pdf (Page 37)

MC68332TUT/D MOTOROLA

37

MOVE.B #$7F,(SYNCR).L ;set system clock to 16.78 MHz

CLR.B (SYPCR).L ;disable software watchdog

INITCS:

* This section initializes two 32K x 8 RAM chips using the Chip Selects.

* The memory starts at address $30000 and is both byte and word readable

* and writable. This program assumes that the RAM chips have access times

* of 85 ns and require no wait states. The DSACK field of the CSOR Registers

* may need to be adjusted for chips that have faster or slower access times.

* The hardware configuration should be similar to that shown in the tutorial

* section entitled “Connecting Memory and Peripherals.” However, when this

* program is loaded into memory using a debugger, CSBOOT must be connected to

* RAM instead of ROM. If CSBOOT is connected to ROM (this is the case with

* the M68332EVK), the code can still be executed if with a BDM debugger such

* as M68ICD32. In this case, manually change the registers using the memory

* modify (mm.w) command.

*******************************************************************

MOVE.W #$0003,(CSBARBT).L ;base address of $00000, block size of 64K

MOVE.W #$7870,(CSORBT).L ;both bytes, R/W, one wait state (if you

;are programming this code into ROM, set

;this field to $6B30).

* Set up chip selects with a base address of $30000, block size of 64K

MOVE.W #$0303,(CSBAR0).L ;set CS0 base addr to $30000, 64K blk

MOVE.W #$0303,(CSBAR1).L ;set CS1 RAM base addr to $30000, 64K blk

MOVE.W #$0303,(CSBAR2).L ;set Chip Select 2 at base addr $30000

MOVE.W #$5030,(CSOR0).L ;set Chip Select 0, upper byte, write only

MOVE.W #$3030,(CSOR1).L ;set Chip Select 1, lower byte, write only

MOVE.W #$6830,(CSOR2).L ;set Chip Select 2, both bytes, read only

MOVE.W #$3FFF,(CSPAR0).L ;set Chip Selects 0,1,2 to 16-bit ports

INITPIT

* This section of code initializes the periodic interrupt timer to interrupt

* every second. Make sure that other code (such as CPU32Bug) hasn't already

* initialized the Vector Base Register to something other than zero.

MOVE.L #CLKINT,($0100).l ;store starting addr of interrupt routine

;at location $100 ($40 X 4).Assume VBR = 0.

MOVE.W #$0640,(PICR).l ;interrupt level 6, vector $40

MOVE.W #$0110,(PITR).l ;time-out period of 1 second

ANDI.W #$F0FF,SR ;mask interrupts below level 6

ORI.W #$0500,SR

ANDI.W #$FFF0,(SIMCR).l ;set interrupt arbitration field to a

ORI.W #$0005,(SIMCR).l ;unique value.

ITSELF

BRA ITSELF ;stay here while waiting for interrupts

CLKINT ;interrupt routine for PIT

ADDI.L #$01,D0 ;instructions in interrupt routine go here

RTE

4.3 Configuring Internal RAM

The internal RAM can be mapped to any 2 Kbyte boundary in the address map, but it must not overlap the

module control registers. The RAM is disabled out of reset. To initialize the RAM, write the desired base

address to the RAM base address and status register (a write-once only register) and clear the RAMDS bit

to enable the RAM. Configure the RASP[1:0] bits in the RAM module configuration register to select the ac-

cess privileges.

If battery backup for the RAM is not used, connect the V

STBY

pin to ground. If backup battery power is used,

consult the

MC68332 User’s Manual

for an explanation of calculating the capacitance needed between the

V

STBY

pin and ground.

When using the ICD32 debugger, make sure not to display any potentially uninitialized memory in the F3

and F6 windows, because the debugger tries to read this memory and will display error messages if it is

uninitialized.

Motorola M68CPU32BUG User Manual Page 37

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