Motorola M68CPU32BUG User Manual download pdf (Page 19)

MC68332TUT/D MOTOROLA

Chip-select access time (MCU read cycle) = (2 + WS) X t

CYC(min)

- t

CLSA(max)

- t

DICL(min)

Chip-select access time (MCU write cycle) = (2 + WS) X t

CYC(min)

- t

CLSA(max)

+ t

CLSN(min)

In the equations, WS is the number of wait states programmed in the DSACK field. For fast termination

mode, WS = -1, for zero wait states, WS = 0, for one wait state, WS = 1, etc. Also, it is assumed that chip-

select assertion is based on address strobe. If it is based on data strobe, add 2(t

CYC

) to t

CLSA

for the write

cycle chip-select access time. The other known parameters are shown in Table 2.

MCU read cycle access time is used to determine the number of wait states needed for a given memory

speed, because it is longer than write cycle access time, and is thus the limiting factor.

As an example, the equations below are solved for zero wait states, assuming 16.78 MHz timing:

Address access time = 2.5 X 59.6 nsec – 29 nsec – 5 nsec = 115 nsec

Chip-select access time (MCU read cycle) = 2 X 59.6 nsec – 25 nsec – 5 nsec = 89.2 nsec

Chip-select access time (MCU write cycle) = 2 X 59.6 nsec – 25 nsec + 2 nsec = 96.2 nsec

The equations can also be solved for the number of wait states needed, given the memory speed. Use Ta-

ble 3 to find the number of wait states required for a particular memory speed. For example, with a 16.78

MHz clock, a memory with a write cycle time of 130 ns requires one wait state, since 130 ns is between 89.2

ns and 148.8 ns.

Table 2 Parameters Needed for Calculating Memory Access Times

Parameter Symbol

16.78 MHz 20.97 MHz

Min Max Min Max

Clock Period

CYC

59.6 nsec --- 47.7 nsec ---

Clock Low to AS, DS, CS Asserted

CLSA

2 nsec 25 nsec 0 23 nsec

Data In Valid to Clock Low (Data Setup)

DICL

5 nsec --- 5 nsec ---

Clock High to Address, FC, SIZE, RMC Valid

CHAV

0 29 nsec 0 23 nsec

Clock Low to AS, DS, CS Negated

CLSN

2 nsec 29 nsec 2 nsec 23 nsec

Table 3 Memory Access Times in Nanoseconds

Wait

States

16.78 MHz 20.97 MHz

Chip-Select Read Access

(Memory Write Access)

Address

Access

Chip-Select Read Access

(Memory Write Access)

Address

Access

F.T. 29.6 55.4 19.7 43.55

0 89.2 115.0 67.4 91.25

1 148.8 174.6 115.1 138.95

2 208.4 234.2 162.8 186.65

3 268.0 293.8 210.5 234.35

4 327.6 353.4 258.2 282.05

5 387.2 413 305.9 329.75

6 446.8 472.6 353.6 377.45

7 506.4 532.2 401.3 425.15

8 566.0 591.8 449.0 472.85

9 625.6 651.4 496.7 520.55

10 685.2 711 544.4 568.25

11 744.8 770.6 592.1 615.95

12 804.4 830.2 639.8 663.65

13 864.0 889.8 687.5 711.35

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 55 56

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