Motorola M68CPU32BUG User Manual download pdf (Page 34)

MOTOROLA MC68332TUT/D

2. If using the software watchdog, periodic interrupt timer, or the bus monitor, select action taken when

FREEZE is asserted. The freeze software enable (FRZSW) bit determines whether the software

watchdog and periodic interrupt timer counters continue to run when FREEZE is asserted, and the

freeze bus monitor enable (FRZBM) bit determines whether the bus monitor continues to operate

when FREEZE is asserted.

3. Select the interrupt arbitration level for the SIM with the interrupt arbitration (IARB) field. The default

state out of reset is $F, the highest precedence. To avoid spurious interrupts, each module request-

ing interrupts must have a unique, non-zero value in the IARB field. The CPU treats external interrupt

requests as SIM interrupts.

4.2.2 Clock Synthesizer Control Register (SYNCR)

SYNCR controls clock frequency, clock reference failure, clock signal usage during low-power stop, and fre-

quency of the 6800 bus clock output (ECLK). Configure SYNCR as follows.

1. Set frequency control bits (W,X,Y) to specify frequency.

2. Select action to be taken during loss of crystal (RSTEN bit): activate a system reset or operate in limp

mode.

3. Select system clock during LPSTOP (STSIM and STEXT bits).

4. If using the ECLK, select the ECLK frequency (EDIV bit).

4.2.3 System Protection Control Register (SYPCR)

SYPCR controls the software watchdog, which is enabled out of reset. This means that, unless the SWE bit

is cleared, a program must write the appropriate service sequence to the software service register (SWSR)

in a defined period or the MCU will reset each time the watchdog times out.

1. Disable the software watchdog, if desired, by clearing the SWE bit.

2. If the watchdog is enabled, perform the following actions.

A. Choose whether to prescale the software watchdog clock (SWP bit).

B. Select the time-out period (SWT bits).

3. Enable the double bus fault monitor, if desired (DATAFE bit or HME bit).

4. Enable the external bus monitor (BME bit) if desired.

5. Select the time-out period for bus monitor (BMT bits).

4.2.4 Periodic Interrupt Timer Register (PITR)

PITR and PICR control the periodic interrupt timer (PIT). The PIT begins to run when a timing modulus is

written to the PITM field in PITR. However, interrupt requests from the PIT are recognized only after an in-

terrupt priority level is written into the PIRQL field in the PICR. Clearing PITM stops the timer; clearing

PIRQL disables interrupts, but the timer continues to run. Because the CPU treats external interrupts as

SIM interrupt requests, PIT interrupts take precedence over external interrupts of the same priority. To use

the timer, proceed as follows.

1. Make certain that there is a vector to the interrupt service routine in the exception vector table, and

that there is a service routine at the address pointed to.

2. Select whether or not to prescale the timer clock signal (PTP bit in PITR).

3. Select the timing modulus or interrupt rate (PITM field in PITR).

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Motorola M68CPU32BUG User Manual Page 34