Motorola M68CPU32BUG User Manual download pdf (Page 43)

MC68332TUT/D MOTOROLA

4.5.2 Parameter RAM Registers

Each channel has a dedicated set of word-long registers (called parameters) in the parameter RAM. TPU

Channels 0 - 13 have five parameters, and channels 14 and 15 have seven parameters. The CPU and the

TPU communicate through the parameter RAM. The meaning of each location in the parameter RAM is de-

fined by the microcode for a particular function.

In the TPU manual, addresses in parameter RAM for channels 0 to 13 are defined as $YFFFW0, $YFFFW2,

$YFFFW6, $YFFFW8, and $YFFFWA. Channels 14 and 15 have the additional parameters $YFFFWC and

$YFFFWE. The “Y” is either an F or a 7, depending on the “MM” bit in the SIM configuration register. Out of

reset, the “Y” is an F. The “W” is the channel number. The last number is the location of the channel param-

eters. For example, out of reset, the first parameter for TPU channel 10 is located at $FFFFA0.

TPULITPAK/D contains programming notes for all the A and G mask functions. See the programming note

that pertains to a particular function for a parameter diagram, field encodings, and a description of the op-

tions that are available.

4.5.2.1 The Channel Control Register

The channel control register (CCR) is a parameter that is common to most functions. It is nine bits long, and

it is usually the first parameter. The CCR allows the CPU to pass information concerning channel configu-

ration to the TPU. The microcode for a particular function determines the meaning of data in the CCR. The

function may or may not use all of the information, because the microcode can configure the channel without

help from the CPU. Usually, the TPU overwrites the CCR after initialization and uses the space for a TPU-

controlled parameter.

In general, the channel control register consists of three fields:

1. The time base select (TBS) field determines which timer count register (TCR) the channel uses. The

channel can match and capture TCR1 and TCR2. The TPU is also capable of matching one TCR and

capturing the other.

2. The pin action control (PAC) field has two basic functions. For an output channel, the PAC field de-

termines what type of transition the pin will make when a match occurs. For an input channel, the

PAC field determines what type of transition the pin will detect.

3. The pin state control (PSC) field determines initial pin state immediately after a host service request.

See the programming note that pertains to a particular function for specific information about the channel

control field.

4.5.3 TPU Interrupts

Several steps must be followed in order for a TPU channel to request interrupt service.

1. Store the starting address of the interrupt service routine in the CPU interrupt vector table.

A. The location in the vector table where the service routine starting address is stored is called the

vector address. The vector address is calculated from the interrupt vector number— it is four times

the vector number plus the value in the vector base register.

B. The interrupt vector number is formed by concatenating a base vector number with the channel

number. Choose a base vector number and write it to bits 7 through 4 in the TPU interrupt config-

uration register (TICR). For example, choosing a base vector number of $80 would assign inter-

rupt vector $80 to channel 0, interrupt vector $81 to channel 1, interrupt vector $82 to channel 2,

and so on, through assignment of interrupt vector $8F to channel 15.

For example, if channel 4 is being set up to request interrupt service, the interrupt vector is $84.

Assuming the vector baseregister holds a value of zero, the vector address is:

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 55 56

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Motorola M68CPU32BUG User Manual Page 43

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