Motorola M68CPU32BUG User Manual download pdf (Page 41)

MC68332TUT/D MOTOROLA

4.5 Configuring the Time Processor Unit

The time processor unit (TPU) is an intelligent, semi-autonomous timer that has16 independently-program-

mable channels. The TPU can run pre-programmed timing functions stored in an internal ROM, or it can run

custom functions. Currently, there are two versions of the TPU, differentiated by the type of pre-pro-

grammed functions in ROM. The version designated MC68332A has an automotive function set, while the

version designated MC68332G has a motion control function set. Table 7 lists the functions in each version.

Pages A-2 and A-3 in the

TPU Reference Manual

show all of the function numbers and other necessary

encodings for each version of the TPU. For more detailed information on how to use each individual TPU

function, order the TPU Literature Pak (TPULITPAK/D) from Literature Distribution.

All versions of the TPU can also run custom functions. However, the internal SRAM in not available for other

purposes when the TPU runs custom functions. There are two ways to run custom functions:

1. Choose between any of the available functions (A mask, G mask, and custom functions available on

Freeware Data Systems). See TPUPN00/D

Using the TPU Function Library and TPU Emulation

Mode

for more information.

2. Write custom functions. Motorola sells a TPU assembler called M68STPUMASMAB. Unlike the pub-

lic domain version available via Freeware Data Systems, the commercial product contains documen-

tation and is fully supported. To assist with debugging, a TPU simulator is available from Ashware—

call (520) 544-0504.

4.5.1 Control Registers

The TPU has several control registers that are shared by all 16 channels. Some of these registers, such as

the channel interrupt enable register and channel interrupt status register, are not always used. However,

the TPU module configuration register, the channel function select registers, the host sequence registers,

the host service request registers, and the channel priority registers should always be initialized.

4.5.1.1 The TPU Module Configuration Register

The TPU module configuration register (TPUMCR) determines important operating characteristics, such as

prescaler values for timer count registers TCR1 and TCR2, and the interrupt arbitration number. It also de-

termines whether TPU registers reside in supervisor space or in user space. The TPUMCR itself resides in

supervisor space. See 4.1 Configuring the Central Processing Unit for more information concerning user

and supervisor space.

Notes:

1. Older versions of the MC68332 that are not designated by an “A” or “G” have the automotive mask set without

the Quadrature Decode function. Otherwise, the functions in the older version are identical to those in the

MC68332A. Code written for the old version will work on the new version.

Table 7 Functions Included In TPU Mask Sets

MASK A

MASK G

Period/Pulse-Width Accumulator (PPWA) Programmable Time Accumulator (PTA)

Output Compare (OC) Queued Output Match (QOM)

Stepper Motor (SM) Table Stepper Motor (TSM)

Position-Synchronized Pulse Generator (PSP) Frequency Measurement (FQM)

Period Measurement with Additional/Missing Tooth Detec-

tion (PMA)

Universal Asynchronous Receiver/Transmitter (UART)

Input Capture/Input Transition Counter (ITC) New Input Transition Counter (NITC)

Pulse Width Modulation (PWM) Multichannel PWM (MCPWM)

Discrete Input/Output (DIO) Hall Effect Decoder (HALLD)

Synchronized Pulse-Width Generation (SPWM) Commutation TPU Function (COMM)

Quadrature Decode (QDEC) Fast Quadrature Decode (FQD)

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 55 56

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