Motorola M68CPU32BUG User Manual download pdf (Page 25)

MC68332TUT/D MOTOROLA

It is very important to make certain that the IRQ7 signal be de-asserted before the level seven interrupt ser-

vice routine ends. A new level seven interrupt will be recognized in the following cases:

If the IRQ7 signal de-asserts and is then re-asserted while the interrupt service routine is executing.

If the IRQ7 signal remains asserted until the RTE instruction that ends the service routine is executed.

If the IRQ7 signal is asserted and the IPL field is written during execution of the interrupt service routine.

This is true even when the mask is re-written to $7.

Provide for de-assertion of the signal within the service routine, and avoid writing to the SR during execution

of the level seven interrupt service routine.

2.10.6 Checklist for External Interrupt Acknowledge

• Is the desired pin configured as an interrupt pin instead of an I/O pin?

The interrupt pins are dual-function pins. Their initial configuration is determined by the state of data

bus pin 9 at the release of reset. After reset, their configuration is determined by the port F pin assign-

ment register.

• Was the starting address of the interrupt routine written to the vector offset address?

The CPU must be told where the interrupt service routine begins. See 4.1.1 Exceptions for a more de-

tailed explanation.

• Is the IARB field in the SIMCR a unique, non-zero value between $1 and $F?

All interrupting modules must have a unique, non-zero value in the IARB field

• Is the IPL field in the CPU status register set to a value lower than the desired interrupt level?

The CPU will not recognize an interrupt that is at the same level or lower than the value in the IPL field.

Level 7 is the only exception to this rule; it is always recognized.

• Is the IACK cycle terminated with AVEC

or DSACK?

The IACK cycle must be terminated by assertion of the AVEC or DSACK signals, or a chip-select circuit

must be configured to assert AVEC or DSACK internally.

• Does the interrupt request signal de-assert inside the exception handler?

It is a good idea to control de-assertion of the interrupt in software. The interrupt should be de-asserted

before the RTE instruction.

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Motorola M68CPU32BUG User Manual Page 25