Motorola M68CPU32BUG User Manual download pdf (Page 24)

MOTOROLA MC68332TUT/D

2.10.4.2 Autovectors

Autovectors can only be used with external interrupt service requests. When an external device cannot sup-

ply a vector number in response to an IACK cycle, an autovector can be used instead.The autovector num-

ber is determined by the priority of the interrupt request. For example autovector number 2 corresponds to

IRQ2. In order for an autovector to be used the IACK cycle must be terminated by an AVEC signal. There

are two ways to do this: either assert the AVEC signal externally or use a chip-select circuit to provide the

AVEC signal internally. Once the bus cycle has been terminated, the CPU saves the current context, loads

the 32-bit vector into the PC, and begins to execute the service routine at that address.

One way to use autovectors is to tie the AVEC pin to ground. This effectively generates an external AVEC

signal in response to all IACK cycles caused by external interrupt service requests. If it is not desirable for

all external interrupts to autovector, specific external devices can assert AVEC in response to an IACK cy-

cle. However, in this case it is usually easier to set up a chip-select circuit to provide the AVEC

signal inter-

nally.

Perform the following steps to set up a chip-select circuit to generate the AVEC signal:

1. Configure the chip-select pin for any of its available functions in the pin assignment register.

2. Program the appropriate base address register to $FFF8 or higher.

3. Select the following fields in the appropriate option register:

A. MODE Bit — select asynchronous mode (%0)

B. BYTE Field— select assertion for both bytes (%11)

C. R/W Field— select assertion for both reads and writes (%11)

D. STRB Bit — select synchronization with AS (%0)

E. DSACK Field — select number of wait states (user specified)

F. SPACE Field — select CPU space assertion (%00)

G. IPL Field — select interrupt priority level (user specified)

H. AVEC Bit— enable AVEC generation (%1).

See 4.2 Configuring the System Integration Module for a more detailed description of the fields in chip-

select option registers.

2.10.5 Level-Sensitive versus Edge-Sensitive Interrupt Pins

Interrupt pins IRQ[1:6] are level sensitive. Assertion of an active-low signal connected to one of these pins

is recognized as a valid interrupt request if the interrupt priority level of the pin is greater than the value of

the IPL field in the CPU status register (SR). Once an interrupt service request is recognized, the SR is cop-

ied onto the stack, then the IPL value is changed to match the priority level of the interrupt being serviced.

This prevents interrupts of the same or lower priority while the service routine executes. For instance, if the

IPL value is $3, and a level five service request is recognized, the SR is stacked, then the IPL value is

changed to $5. An RTE instruction at the end of the service routine normally terminates interrupt service.

RTE pops the stacked SR, and thus restores the original IPL value. The IPL field can also be changed by

writing to the SR. If an interrupt service routine writes a lower value to the IPL field while the request signal

is still asserted, the CPU recognizes a second service request. Avoid changing the IPL value during execu-

tion of the interrupt service routine.

IRQ7 is both edge and level sensitive. Level seven interrupts cannot be masked by the IPL field. When a

level seven interrupt service request is recognized, the current value of the status register is pushed onto

the stack, and the IPL value is changed to $7.

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Motorola M68CPU32BUG User Manual Page 24

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