Motorola MVME712A/D3 User Manual Page 96
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Test Descriptions
3-52 167Bug Debugging Package UserÕs Manual
3
Timer 2 Interrupts - TMR2E
Verifies that level 0 interrupts will not generate an interrupt, but will set the
appropriate status. Then verifies that all interrupts (1 through 7) can be
generated and received and that the appropriate status is set.
Command Input:
167-Diag>PCC2 TMR2E
Response/Messages:
After the command has been issued, the following line is printed:
PCC2 TMR2E: Timer 2 Interrupts.............. Running --->
If all parts of the test are completed correctly, then the test passes.
PCC2 TMR2E: Timer 2 Interrupts.............. Running ---> PASSED
If any part of the test fails, then the display appears as follows:
PCC2 TMR2E: Timer 2 Interrupts.............. Running ---> FAILED
PCC2/TMR2E Test Failure Data:
(error message)
Here, (error message) is one of the following:
Interrupt Control Register did not clear
Address =________, Expected =__, Actual =__
Interrupt Enable bit did not set
Address =________, Expected =__, Actual =__
Interrupt Status bit did not set
Status: Expected =__, Actual =__
Vector: Expected =__, Actual =__
State : IRQ Level =_, VBR =__
Incorrect Vector type
Status: Expected =__, Actual =__
Vector: Expected =__, Actual =__
State : IRQ Level =_, VBR =__
Unexpected Vector taken
Status: Expected =__, Actual =__
Vector: Expected =__, Actual =__
State : IRQ Level =_, VBR =__
Incorrect Interrupt Level
Level : Expected =_, Actual =_
State : IRQ Level =_, VBR =__
- (MVME167BUG/D3) 1
- Restricted Rights Legend 2
- Contents 5
- List of Figures 10
- List of Tables 11
- 167BUG GENERAL 13
- INFORMATION 13
- Description of 167Bug 15
- 167Bug General Information 16
- (Sheet 1 of 3) 20
- (Sheet 2 of 3) 21
- (Sheet 3 of 3) 22
- MVME167BUG/D3 23
- MVME167BUG/D3 1-13 25
- 166BBug Implementation 26
- Execute User Program 27
- Setup System Parameters 28
- Memory Requirements 29
- Diagnostic Facilities 29
- Related Documentation 30
- Manual Terminology 31
- DIAGNOSTIC FIRMWARE 33
- Diagnostic Monitor 34
- Command Entry and Directories 35
- Utilities 36
- MVME167BUG/D3 2-5 37
- Help - Command HE 38
- Help Extended - Command HEX 38
- Figure 2-1. Help Screen 39
- Loop Always Mode - Prefix LA 40
- Loop-Continue Mode - Prefix LC 40
- Loop-On-Error Mode - Prefix LE 40
- Non-Verbose Mode - Prefix NV 41
- Stop-On-Error Mode - Prefix SE 42
- Self Test - Command ST 42
- Zero Pass Count - Command ZP 43
- Diagnostic Firmware 44
- TEST DESCRIPTIONS 45
- Memory Addressing - ADR 47
- Alternating Ones/Zeros - ALTS 48
- Bit Toggle - BTOG 49
- Code Execution/Copy - CODE 51
- Data Patterns - PATS 52
- Permutations - PERM 55
- Quick Write/Read - QUIK 56
- Memory Refresh Testing - REF 57
- Random Data - RNDM 59
- MK48T0x (RTC) Tests 60
- BBRAM Addressing - ADR 61
- Clock Function - CLK 62
- MVME167BUG/D3 3-19 63
- RTC not running 63
- Data Miscompare Error: 63
- Battery Backed-Up SRAM - RAM 64
- Prescaler Clock Adjust - ADJ 66
- FAST Bit - FAST 67
- GPIO Interrupts - GPIO 68
- LANC Interrupts - LANC 70
- MIEN Bit - MIEN 72
- Prescaler Clock - PCLK 73
- Device Access - REGA 84
- Register Access - REGB 85
- Timer 1 Counter - TMR1A 86
- Timer 1 Free-Run - TMR1B 87
- Timer 1 Interrupts - TMR1E 90
- Timer 2 Counter - TMR2A 92
- Timer 2 Free-Run - TMR2B 93
- Timer 2 Interrupts - TMR2E 96
- Vector Base Register - VBR 98
- Check-Bit DRAM - CBIT 101
- Test Descriptions 102
- Failures in checkbit memory: 102
- The test ends with: 102
- Exceptions - EXCPTN 103
- Multi-Bit-Error - MBE 104
- Single-Bit-Error - SBE 105
- Scrubbing - SCRUB 106
- Bus Clock Register - BUSCLK 110
- Chip ID Register - CHIPID 111
- MVME167BUG/D3 3-71 115
- Data Cache Copyback - DCAC_CB 117
- Serial Port (ST2401) Tests 122
- MVME167BUG/D3 3-79 123
- MVME167BUG/D3 3-81 125
- 167-Diag>ST2401 DMA 126
- MVME167BUG/D3 3-83 127
- MVME167BUG/D3 3-85 129
- 167-Diag>ST2401 INTR 130
- MVME167BUG/D3 3-87 131
- ST2401 Error Messages 132
- Build Default Tables - TBLBLD 136
- MVME167BUG/D3 3-93 137
- 167-Diag>MMU TBLVERF 137
- TC Register Test - TC 138
- RP Register Test - RP 139
- Tablewalk Mapped Pages - WALK 140
- Mapped ROM Read Test - MAPROM 141
- Used Page Test - USEDPAGE 142
- Modified Page Test - MODPAGE 143
- Invalid Page Test - INVPAGE 144
- Register Access - REGA 147
- Register Walking Bit - REGB 148
- VME2/REGB Test Failure Data: 149
- MVME167BUG/D3 3-107 151
- Timer Accuracy Test - TACU 156
- Prescaler Clock Adjust - TMRC 159
- Overflow Counter - TMRH, TMRI 162
- Watchdog Timer Counter - TMRJ 163
- Register Access - REGACC 166
- Local Walking Bit - L_WKB 167
- MVME167BUG/D3 3-129 173
- Mnemonic Description 173
- REG Deltapath test 173
- IRQ Interrupt test 173
- PI/T Port's IRQ - IRQ 175
- 167-Diag>CF LANC 178
- Chip Self Test - CST 179
- (error message) 180
- MVME167BUG/D3 3-137 181
- MVME167BUG/D3 3-141 185
- RECEIVE Data Time-Out 185
- +12VDC Fuse - FUSE 190
- Internal Loopback - ILB 191
- Interrupt Request - IRQ 194
- MVME167BUG/D3 3-151 195
- 167-Diag>LANC MON 195
- Additional Error Messages 198
- Device Access - ACC1 202
- Register Access - ACC2 204
- DMA FIFO - DFIFO 206
- Interrupts - IRQ 207
- Loopback - LPBK 210
- SCRIPTs Processor - SCRIPTS 211
- SCSI FIFO - SFIFO 214
- MVME167BUG 215
- ENVIRONMENT 215
- Configure VMEbus Interface 221
- MVME167BUG/D3 4-17 231
- MVME167Bug Environment 232
- Numerics 233
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