Motorola MVME712A/D3 User Manual download pdf (Page 162)

Test Descriptions

3-118 167Bug Debugging Package UserÕs Manual

Overﬂow Counter - TMRH, TMRI

This test enables the overflow counter and a count of timer overflow is

expected to accumulate. The COVF bit in the timer control register is asserted

and OVF bit is verified to be clear. The timer counter register is set to zero, the

timer compare register is loaded with the value $55aa, and the timer is

enabled. When TIC(1/2) becomes true, the timer is disabled and the timer

overflow counter register is checked to see that the resultant overflow was

counted. TMRH specifies Tick Timer 1 Overflow Counter. TMRI specifies

Tick Timer 2 Overflow Counter.

Command Input:

167-Diag>VME2 TMRH

or:

167-Diag>VME2 TMRI

Response/Messages:

Note that in all responses shown below, the response "TMR

: Timer

" is TMRH:

Timer 1

or TMRI: Timer 2, depending upon which test set is being performed.

After the command has been issued, the following line is printed:

VME2 TMR

: Timer

Overflow Counter......... Running --->

If all parts of the test are completed correctly, then the test passes:

VME2 TMR

: Timer

Overflow Counter......... Running ---> PASSED

If any part of the test fails, then the display appears as follows:

VME2 TMR

: Timer

Overflow Counter......... Running ---> FAILED

(error message)

Here, (error message) is one of the following:

Timer ____: Overflow Counter did not clear.

Timer Control Register = ________

Tick Timer ____: Counter did not clear.

Timer Counter Register = ________/________ (address/data)

Tick Timer ____: timeout waiting for ITIC____

Tick Timer ____: Overflow counter did not increment

Timer Control Register = ________

1 2 ... 157 158 159 160 161 162 163 164 165 166 167 ... 238 239

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Motorola MVME712A/D3 User Manual Page 162