MEMC040 Memory Controller (MEMC1/MEMC2) Tests
MVME167BUG/D3 3-71
3
If during a FAT, a data miscompare error occurs when testing BAD bits:
RAM control register set to ________ but incorrect data read
Address =________, Expected =________, Actual =________
If during a FAT, if no bus error occurs when accessing below the base address:
RAM exists below base address of ________
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