Motorola MCP750 Specifications download pdf (Page 96)

evice Driver Programming

7-4

Processor Board 7

Figure 7-1 and Figure 7-2 give an overview of the main architectural features of the Power

Hawk 620/640 processor boards. The Power Hawk 620 processor board hosts a single

processor. The Power Hawk 640 hosts either a single processor or a dual processor. Both

the Power Hawk 620 and Power Hawk 640 contain various amounts of memory, an

optional L2 cache, I/O interface, various bridge chips, real-time clocks, UART, Ultra-

SCSI interface, etc.

The Power Hawk 620/640 processor cycle time is 5 nanoseconds (200 MHz) and is

capable of executing four instructions per cycle. The processor data bus is 64-bits wide to

accommodate two 32-bit instructions per cycle.

There are separate 16-KB, four-way set-associative instruction and data caches.

Instruction cache coherency is maintained in the software; bits in the instruction cache

indicate whether a cache block is valid or not. Four-state data cache coherency (MESI) is

maintained in the hardware. Secondary data cache support is provided. Caches can be

disabled in software. They can also be locked and parity checked.

Refer to either the Motorola MVME 2600 Architecture Manual or the Motorola MVME

4600 Architecture Manual for additional details on the processor boards.

Memory 7

The Power Hawk 620/640 uses 32-bit addresses for up to 4 GB of virtual address space.

As shown in Figure 7-1 and Figure 7-2 the processor(s) has cached access to local

memory. The processor memory bus rate of 66.666MHz provides the bandwidth required

by the processors. Local memory resides on the processor daughter card and can be either

64MB or 128MB with ECC (Error Correction Capability).

The Power Hawk 620/640 memory architecture also supports an Error Detection and

Correction (EDAC) mechanism. This mechanism detects and recovers from single-bit

errors automatically. However, multiple-bit errors are inherently unrecoverable. The

EDAC mechanism detects multiple-bit error(s) only upon the ﬁrst read access (of any size)

from a corrupted memory location. There is no error correction possible in this case. The

EDAC handles the error by raising a precise hardware exception to the processor which

initiated the access. Consequently, the operating system panics and halts the system.

Buses 7

There are two main busses on the Power Hawk 620/640: the processor bus and the 64-bit

PCI bus.

The processor bus is a dedicated high-performance bus on the processor mezzanine board.

This is supplemented by an industry-standard PCI bus, which is the main bus connecting

the ISA devices, and SCSI, VME, and network adapter interfaces to the processor.

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Motorola MCP750 Specifications Page 96