Motorola MCP750 Specifications download pdf (Page 88)

evice Driver Programming

6-10

powerfail, 60 Hz clock, timers, real-time clocks, the console processor, serial or parallel

port controllers, and so on. Software interrupt sources include inter-processor interrupts,

the softclock interrupt, and context switch interrupts.

Interrupt Lines (Levels) 6

On the VME I/O bus, the bus lines carrying the interrupt signal from an interrupt requester

to a processor are called interrupt lines. The VME chassis supports 7 interrupt levels. On

the I/O bus, these are labeled IRQ1-7*.

VME interrupt request lines are only one source of interrupts in the system. VME inter-

rupt request lines are mapped to the PowerMAXION system’s interrupt levels. For addi-

tional details and a list of priority levels and the mapping of interrupt sources to these lev-

els, refer to the PowerMAXION Architecture Manual.

Following are some additional characteristics of the PowerMAXION interrupt levels.

The hardware interrupt priority determines the relative urgency of servicing the event

within the overall system.

Interrupt priorities are set hierarchically and statically in hardware. For each interrupt

level, the device on the highest interrupt level with the lowest slot number has the highest

priority.

If two interrupt requests occur on the same interrupt level simultaneously on the VME I/O

bus, the system resolves the contention as follows:

1. Among devices sharing the same interrupt level on the same I/O bus, the

device with the lowest slot number has the highest priority.

2. Among interrupt levels on the same I/O bus, the device connected to level 7

has the highest priority down to level 1, which has the lowest priority.

3. Among all interrupt sources in the system, the interrupt priority of the

device is predetermined in hardware by its mapping to the PowerMAXION

interrupt levels.

NOTE

For system performance and proper device operation, if a device

is time-critical in that it expects response to an interrupt to be

quick, it should be moved to a higher priority. Devices that can

tolerate longer interrupt latencies—that is, devices whose inter-

rupts can wait for a longer time before being serviced—should be

assigned to a lower priority.

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Motorola MCP750 Specifications Page 88