Motorola MCP750 Specifications download pdf (Page 42)

evice Driver Programming

3-4

of the configuration space. The remaining 192 or 1984(2048-64) is reserved for custom

use by the device.

Within the conﬁguration space of a PCI device/function 28 of the 64 bytes are reserved for

Base address registers(BAR’s). These are read/write registers that are used to set the start-

ing I/O and Memory space address for any additional resources required by the device.

The type and the size of the resource is determined by the read-only portion of each Base

Address register(BAR). PowerMax scan’s all devices connected to the PCI bus when the

system is booted. When PowerMax scans a PCI device it queries the BAR to determine

the resources required. If PowerMax can satisfy the requirements the OS reserves the nec-

essary resources and writes the appropriate base address value into BAR.

The configuration space of PCI is generally accessed via a special hardware mechanism

and does not generally appear as a directly accessible memory region. A device’s conﬁg-

uration space is accessed via a Type 0 conﬁguration cycle while devices connected via PCI

bridges are accessed using Type 1 conﬁguration cycles. When a Type 1 cycle reaches it’s

final destination PCI bus it is converted to a Type 0 configuration cycle. Thus a normal

PCI device must only need to respond to Type 0 conﬁguration cycles without regard to it’s

actual placement within the PCI architecture.

Base Address Registers(BAR) 3

Decode into I/O Space 3

The PowerPC architecture does not allow for a separate I/O space as is allowed in the x86

family which the PCI bus was originally designed for. Thus to access those I/O mapped

resources made available by various PCI devices a region of PowerPC memory space is

dedicated to mapping memory accesses into PCI I/O accesses.

The I/O access region is automatically allocated by the PowerMax OS and requisite reser-

vations are provided for to allow all I/O Base Address Registers of each device to be

accessed by the driver.

The I/O access region is normally allocated in virtual memory page multiples to remove

the possibility of driver or device conﬂicts.

As with all non-memory cycles the PowerPC cache is inhibited, but the write posting pipe-

line is not. To inhibit the possible effect of the write reordering the user must use the

appropriate PowerPC ﬂush instructions after writing each I/O location.

The ﬂush instructions described above are included within the byte swapping macro’s pro-

vided.

Decode into Memory Space 3

The memory region is a cache inhibited area where the appropriate Base Address Regis-

ters are assigned to. This area has many of the same characteristics of the I/O space

described previously. These characteristics include page alignment, and the same need for

pipeline ﬂushing on writes.

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Motorola MCP750 Specifications Page 42