Motorola MCP750 Specifications download pdf (Page 68)

evice Driver Programming

5-4

individually enable and disable them. It sends the resultant interrupt through the MPC105

Bridge chip to the PowerPC 604 processor.

The VMEchip2 initially handles VMEbus interrupts, and can individually enable and

disable them. The chip routes them through the PCI bus to the ISA Bridge chip, which

resolves the interrupts into one of sixteen levels.

Data Types 5

The Power Hawk 610 system supports the following data types:

• Byte (8 bits)

• Half-Word (16 bits)

• Word (32 bits)

• Doubleword (64 bits)

The Power Hawk 610 is a 64-bit machine, but this manual uses the term word for sixteen

bits and longword for 32 bits to remain compatible with other industry-standard systems.

Byte-Ordering and Alignment 5

The Power Hawk 610 orders bytes according to the Big Endian convention, in which the

most significant byte (MSB) always has the lowest address. This provides consistent

addressing independent of the machine word size, as Figure 5-2.depicts (Note that the bit

ordering depicted (with bit 31 most signiﬁcant) applies to I/O addressing. The bit ordering

of the PowerPC 604 is the opposite (with bit 0 most significant). Byte ordering for both

I/O and the PowerPC 604 is the same.)

During I/O transfers, the system expects the addresses of all words to be even addresses—

that is, zero, two, four, six, eight, and so on. Similarly, the system expects that all long-

word addresses are divisible by four—that is zero, four, eight, twelve, and so on. Finally,

the system expects all double-longword addresses to be divisible by eight—that is, zero,

eight, sixteen, and so on.

NOTE

Starting an I/O transfer using non-aligned data types in a driver

program causes a fatal exception error on the Power Hawk 610. In

other words, the hardware cannot recover from alignment errors.

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Motorola MCP750 Specifications Page 68