Motorola MCP750 Specifications download pdf (Page 41)

The PCI Environmen

3-3

Endian translation is necessary whenever a memory or I/O mapped address space is

accessed, or when accessing conﬁguration space in data widths less than 32 bits.

To provide a common mechanism of byte swapping, the BUSGETSR, BUSGETLR, BUS-

PUTSR and BUSPUTLR macros are provided in the xxxx.h header ﬁle.

RISC Vs CISC CPU Processor Issues 3

Generally RISC processors behave in a similar fashion to CISC processors except in two

areas.

RISC processors generally require that a data item must be addressed on a native

address boundary. For example, a 4 byte access must occur on an address boundary that is

evenly divisible by 4.

The second difference is instruction reordering, this aspect of RISC processors is a feature

of the large number of general purpose registers in the design When a particular register

is still busy being manipulated by a instruction a subsequent instruction can proceed as

long as it deals with a non-busy register. This can cause I/O or memory accesses to be

executed out of order with respect to the designers intent.

To overcome endian and reordering issues the designer should use the byte swapping and

i/o ﬂushing macros described previously in the Big verses little endian section.

Types of PCI Resources 3

Conﬁguration Space 3

The PCI conﬁguration space is a mechanism by which the PCI bus conﬁgures virtually all

other characteristics of the devices installed. It allows the Plug and Play nature of PCI bus

to become a reality. Allowing a system to dynamically assign system resources to the

devices that are installed or plugged into a PCI bus somewhere on the system. PCI devices

can be arranged in a virtually unlimited number of conﬁgurations, where some devices are

directly installed in the system while others are located in PCI expansion busses behind

PCI to PCI bridges. Each PCI to PCI bridge has been configured by PowerMax at IPL

time to forward all necessary I/O, memory, interrupts, and configuration accesses for the

PCI devices it bridges automatically. Care must be taken not to override the system set-

tings of PCI devices using mechanisms not provided. To do otherwise would cause con-

ﬂicts with other PCI devices in an unpredictable manor.

The PCI conﬁguration space is broken up into 256 Buses with 32 slots, and 8 functions per

slot. Each function has up to 256 bytes of configuration information. Some devices can

forgo the use of the additional functions and utilize the entire 2048 byte range assigned to

each PCI slot. The PCI speciﬁcation only deﬁnes the ﬁrst 64 bytes of each slot or function

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Motorola MCP750 Specifications Page 41