Motorola MCP750 Specifications download pdf (Page 52)

evice Driver Programming

4-4

Byte-Ordering and Alignment 4

The Series 6000 platform orders bytes according to the Big Endian convention, in which

the most significant byte (MSB) always has the lowest address. This provides consistent

addressing independent of the machine word size, as Figure 4-2 depicts. (Note that the bit

ordering depicted (with bit 31 most signiﬁcant) applies to I/O addressing. The bit ordering

of the PowerPC 604 is the opposite (with bit 0 most significant). Byte ordering for both

I/O and the PowerPC 604 is the same.)

During I/O transfers, the system expects the addresses of all words to be even addresses—

that is, zero, two, four, six, eight, and so on. Similarly, the system expects that all long-

word addresses are divisible by four—that is zero, four, eight, twelve, and so on. Finally,

the system expects all double-longword addresses to be divisible by eight—that is, zero,

eight, sixteen, and so on.

NOTE

Starting an I/O transfer using non-aligned data types in a driver

program causes a fatal exception error on all Series 6000 plat-

forms. In other words, the hardware cannot recover from align-

ment errors.

Figure 4-2. Big Endian Bit and Byte Notation

(H)VME Addressing 4

This section describes the characteristics of data transfers on the (H)VME bus. Doing so

aids in building device addresses and understanding the error detection and recovery fea-

ture of the VMEbus.

LOW

ADDRESS

HIGHER

ADDRESS

LOW ADDRESS = MSB

MSB

LSB

MSB

LSB

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 343 344

No comments

Motorola MCP750 Specifications Page 52