Motorola MCP750 Specifications download pdf (Page 49)

4-1

Chapter 4Series 6000 Hardware Environment

This chapter provides hardware-specific information useful in developing device drivers

for the Series 6000 computer systems. The Series 6000 covers models HN6200 and

HN6800; the text points out model-specific information. This chapter also explains how

hardware conﬁguration affects I/O function and performance.

Some hardware information applies to every driver—for instance, I/O error handling

(affects power failure, alignment errors, controller errors, and bus hangs.) Some informa-

tion differs according to the technique by which the device driver communicates with the

processor—for example, programmed I/O, interrupts, and direct memory access (DMA).

Other information relates as much to software as hardware, such as addressing, byte order-

ing and alignment, word sizes, and conﬁguring arbitration levels and assigning arbitration

priorities.

Communicating with devices via interrupts also poses questions about sharing and conﬁg-

uring interrupt levels to ensure adequate performance levels. Finally, other questions arise

when communicating with devices via DMA—for example, cache coherency, buffering

and addressing.

The first part of this chapter introduces the main architectural features of the platform in

terms of its system and I/O architecture: processors, memory and I/O expansion and con-

figuration. The second part examines hardware issues more closely including physical

addressing, I/O bus timeout, conﬁguring I/O interrupt request levels and associated priori-

ties, and assigning interrupt vectors.

System Overview 4

Series 6000 systems are multiprocessor, real-time, super-microcomputers. They use Sym-

metric Superscalar

Reduced Instruction Set Computer (RISC) microprocessors from

IBM/Motorola, the PowerPC 604.

Processor Board 4

Figure 4-1 depicts the main architectural features of the HN6800 computer system. The

HN6800 computer system can contain up to four processor boards. A processor board

hosts up to two processors, local memory module board, I/O interface, timers, real-time

clocks, UART, and associated components.

The processor clock speed is 150 or 200 MHz (depending on model) and can execute four

instructions per cycle. The processor data bus is 64-bits wide to accommodate two 32-bit

instructions per cycle. The HN6200 or HN6800 Architecture Manual describes the proces-

sor board in greater detail.

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Motorola MCP750 Specifications Page 49