Motorola MCP750 Specifications Page 149
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Developing a Device Drive
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10-3
Programmed I/O Support 10
A programmed I/O device does not directly access physical memory. Instead the device
supplies data to the CPU only when the CPU reads the data directly from device registers.
Data read from a programmed I/O device can be placed in the user’s I/O buffer via the
buffer’s virtual address, which is supplied on a call to the driver’s read routine.
Consult the technical reference manual for your board to determine whether it is a pro-
grammed I/O device.
Data Chaining Support 10
Often, a device must perform DMA transfers that are physically discontiguous. While the
virtual address space assigned to a buffer is contiguous, it might be made up of discontig-
uous physical memory pages.
To accommodate efficient transfers between the device and discontiguous physical mem-
ory, a device sometimes supports data chaining, or scatter/gather I/O. On a gather opera-
tion, the device reads from a number of discontiguous physical memory locations and
transfers the data to the device via DMA. On a scatter operation, the device writes device
data to a number of discontiguous physical memory locations via DMA. Examples of
devices supporting scatter/gather I/O are the HSA and the Interphase V/Ethernet 4207
Eagle device.
Consult the device technical reference manual for your board to determine whether the
device supports this feature. This features greatly simplifies the programming of DMA
operations in the device driver and allows for more efficient data transfer. Refer to
Chapter 12 (“Supporting Direct Memory Access (DMA)”) for an explanation of the pro-
gramming issues related to DMA transfers.
Installing and Testing the Device 10
The purpose of this section is to show how to install your VME device into the Series 6000
platform. Once you have installed your VME device, this section shows how to test the
functionality of the device using the console processor.
- Device Driver Programming 1
- Syntax Notation 4
- Referenced Publications 4
- Contents 7
- Introduction 17
- Organization of Manual 1 20
- Supporting Documentation 1 21
- Understanding Device Drivers 23
- Structure 2 26
- Parallel Execution 2 27
- Interrupts 2 27
- Types of Devices 2 29
- STREAMS Interface 2 30
- Major and Minor Numbers 2 31
- Driver Environment 2 34
- • Master 35
- • System 35
- Master File 2 35
- Driver Development 2 36
- The PCI Environment 37
- Big Vs Little Endian Issues 3 40
- Types of PCI Resources 3 41
- Base Address Registers(BAR) 3 42
- PowerMax OS Support 3 43
- System Overview 4 49
- Caches 4 50
- Memory 4 51
- Data Types 4 51
- (H)VME Addressing 4 52
- Transfer Width Support 4 53
- Address Types 4 53
- Address Modifiers 4 53
- HVME Address Ranges 4 54
- VME Address Ranges 4 54
- Bus Time-Out 4 56
- Bus Arbitration 4 57
- • Straight priority 58
- • CPU Release on Request 58
- Interrupt Lines (Levels) 4 59
- • jumpers or switches 60
- System Overview 5 65
- Caches 5 66
- Memory 5 67
- Timers 5 67
- Interrupts 5 67
- Data Types 5 68
- Byte-Ordering and Alignment 5 68
- VME Addressing 5 69
- Address Modifiers 5 70
- VME Address Ranges 5 70
- Bus Time-Out 5 71
- • Invalid transfer 72
- Bus Arbitration 5 73
- Interrupt Lines (Levels) 5 74
- VME to PCI Address Decode 5 76
- System Overview 6 79
- Caches 6 80
- Memory 6 81
- Data Types 6 81
- VME Addressing 6 82
- Transfer Width Support 6 83
- Address Types 6 83
- Address Modifiers 6 83
- VME Address Ranges 6 83
- VME Devices as Bus Masters 6 84
- Bus Time-Out 6 85
- Bus Arbitration 6 87
- Interrupt Lines (Levels) 6 88
- System Overview 7 93
- Processor Board 7 96
- Memory 7 96
- Timers 7 97
- Interrupts 7 97
- Data Types 7 97
- Byte-Ordering and Alignment 7 98
- VME Addressing 7 99
- VME Address Ranges 7 100
- Bus Time-Out 7 101
- Bus Arbitration 7 102
- Bus Request Levels 7 103
- Interrupt Lines (Levels) 7 103
- PCI Address Decode 7 105
- 0xC0000000 106
- 0xFCC00000 106
- 0xFCFF0000 106
- 0x80000000 106
- 0xA0000000 106
- SYSTEM OVERVIEW 8 109
- PROCESSOR BOARD 8 109
- MEMORY 8 110
- BUSSES 8 112
- TIMERS 8 112
- INTERRUPTS 8 112
- DATA TYPES 8 113
- BYTE-ORDERING AND ALIGNMENT 8 113
- System Data Structures 9 123
- Header Files 9 124
- The cdevsw Structure 9 125
- The cred Structure 9 127
- The adapter Structure 9 129
- Kernel Support Routines 9 132
- BREAK signal.) 133
- Memory Access Routines 9 135
- Address Management Routines 9 135
- Data Transfer Routines 9 136
- Synchronization Routines 9 137
- Sleep Locks 9 138
- Timing and Timeout Routines 9 139
- Interrupt Vector Routines 9 140
- Debug Routines 9 141
- Developing a Device Driver 145
- Device Registers 10 148
- Command Sequences 10 148
- DMA Support 10 148
- Programmed I/O Support 10 149
- Data Chaining Support 10 149
- Installing the Device 10 150
- Initialization Routines 10 153
- I/O Service Routines 10 153
- Interrupt Service Routines 10 153
- The Init Routine 10 155
- The Open Routine 10 157
- • Enable device interrupts 158
- • Lock a non-sharable device 158
- The Close Routine 10 159
- The Read Routine 10 160
- /* number of bytes to copy */ 161
- The Write Routine 10 162
- The Ioctl Routine 10 163
- The Chpoll Routine 10 164
- • 0 if the poll is successful 164
- The Mmap Routine 10 165
- Local Routines 10 168
- Error Handling 10 169
- Protecting a Device Driver 11 175
- • Global variables 176
- • Hardware registers 176
- • _LOCKTEST 178
- • _MPSTAT 178
- Spin Locks 11 179
- Basic Locks 11 180
- NULL pointer 181
- Read/Write Locks 11 183
- Sleep Locks 11 187
- LWP that suc 191
- Using Multiple Locks 11 192
- Synchronization Variables 11 192
- LWP upon 194
- LWP which is in 194
- LWP goes to sleep. No spin 194
- LWPs are sleeping on 196
- LWPswake 196
- Overview 12 199
- DMA into User Buffers 12 199
- 24-Bit DMA Devices 12 203
- Loadable Modules 205
- The DLM Mechanism 13 208
- Demand Load 13 209
- Auto Load 13 209
- Demand Unload 13 210
- Auto Unload 13 210
- Making Modules Loadable 13 211
- Wrapper Data Structures 13 212
- Wrapper Macros 13 212
- Sample Wrapper Code 13 213
- Managing Loadable Modules 13 218
- Unloading the Module 13 220
- DLM Error Messages 13 220
- Dynamic Symbols and kdb 13 220
- Using idtools 14 223
- Overview of DSP Components 14 229
- DSP Component Files 14 230
- Driver.o 14 231
- Master 14 231
- System 14 231
- $version 1 232
- $loadable gt 232
- Mtune 14 233
- Sassign 14 235
- Space.c 14 236
- Packaging the Driver 14 237
- Installing a Package 14 240
- Removing a Package 14 241
- Installing a DSP 14 241
- Updating a DSP 14 242
- Removing a DSP 14 242
- Building a New Kernel 14 243
- Driver Testing and Debugging 245
- General Guidelines 15 248
- Common Driver Problems 15 251
- Timing Errors 15 252
- Corrupted Interrupt Stack 15 252
- Accessing Critical Data 15 252
- Booting Scenarios 15 255
- Shutdown and Reboot 15 255
- Using crash Functions 15 263
- Kernel Debugger 15 264
- Entering kdb from a Driver 15 265
- System Panics 15 265
- Special Considerations 267
- Additional Considerations 16 272
- System Requirements 16 272
- P_PLOCK 278
- Shared Memory Regions 17 282
- User I/O Buffer Descriptor 17 283
- Overview of Error Returns 17 289
- Driver 17 291
- The spl Support Routines 17 295
- Rescheduling Control Tools 17 296
- The Server System Calls 17 297
- The open Routine 17 299
- The aread Routine 17 302
- The awrite Routine 17 303
- The acheck Routine 17 304
- The await Routine 17 305
- Control Functions 17 306
- The close Routine 17 307
- Use of Local Memory 17 312
- MPA_CPU_VMELEV command; 313
- P_SHMBIND 315
- Reset the Device 17 316
- Debugging the Driver 17 317
- Glossary 325
- Glossary-12 336
- I/O 10-7 338
- STREAMS interface 2-6 338
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