Motorola MCP750 Specifications download pdf (Page 312)

evice Driver Programming

17-36

the process is in this state, all signals are ignored. The process no longer

executes at normal program level. Each time the connected interrupt

becomes active, the CPU that is receiving the interrupt switches to the

context of the connected interrupt process within the kernel. The kernel

then jumps to the beginning of the interrupt-handling routine with the

connected interrupt still active. Although the connected interrupt is active,

the process executes in user mode rather than kernel mode; all of the

process’s virtual address space previously locked into physical memory is

accessible.

User-Level Interrupts and Memory Locking 17

Any memory location that is accessed from a user-level interrupt routine must be locked in

memory. If a page fault occurs while at interrupt level because of an access to a non-

resident memory location, the system halts. The application can either lock all the memory

of the user-level interrupt process or selectively lock only the pages that are referenced by

the user-level interrupt routine. If selective locking is used (see userdma(2)), the

following memory accesses must be considered:

• The instructions of the user-level interrupt routine.

• Any shared regions which are referenced by the user-level interrupt

routine.

• The memory used for the user-level interrupt routine's stack.

• The C library's interrupt stub which is executed prior to the interrupt

routine. Note that the iconnect(3C) call supports a function code

(ICON_LOCK) for locking this section of code.

Use of Local Memory 17

If you want to use local memory with user-level interrupt processes on a Series 6000

system with more than one CPU board, you must follow the procedure that is explained in

the paragraphs that follow. A complete discussion of the issues related to the use of local

memory with user-level interrupt processes is provided in the PowerUX Real-Time Guide.

If a process binds some portion of its address space to local memory and then issues the

iconnect(3C) and ienable(3C) calls in order to connect to an interrupt, the CPU

that processes the interrupt might not be located on the same CPU board where the

process's address space bindings were created. In this case, some of the local memory

references that were not previously remote might now become remote memory references.

Similarly, some of the previously remote local memory references might now no longer be

remote references. In these cases, data incoherences can occur when the user-level

interrupt process references these portions of its address space.

Note that remote memory references are not an issue on Series 6000 systems that have

only one processor board.

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Motorola MCP750 Specifications Page 312