Motorola M68000 User's Guide Page 221

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The 68030 207
easy to take a binary logical address and partition it into a page number
and an offset within the page.
Logical Address (example)
31 10 S 0
offset
Since addresses on the 68030 are all 32 bits, we can divide the logical
address into two pieces as long as the sizes add up to 32. For example, if
we desire pages to be IK (1024 bytes), the offset requires 10 bits, leaving
22 bits for the page number. Therefore, there would be 222 pages, each
1024 bytes long.
How do we then map the pages into the corresponding physical page
frames? Also, what if all the pages are not currently in memory? When we
implement a virtual memory, we store the pages that are not currently in
memory on a secondary storage device such as a disk. The hardware must
be aware of what pages are actually in physical memory at a given time.
Both of these problems are solved by the use of a page table. A page table
is simply a translation table. The physical frame number corresponding
to a particular page can be found by looking it up in the page table. A
simple organization of a page table is that of an array of frame numbers.
The page number is used as an index into the array.
The problem of determining if a page is currently mapped to physical
memory is solved by providing an extra bit with each page table entry.
This bit can be set if the frame number is valid and reset if the page
is not in memory. In the latter case, the frame number can be used to
provide information to the operating system about where the page is
located on secondary storage. The hardware doesnt handle this case. The
hardware only handles the mapping of pages to physical memory. What
the hardware does when it encounters a non-resident page is to generate
a page fault. This page fault is detected by the operating system, the
missing page is brought into memory, and the instruction that caused the
page fault is allowed to continue. This time it will find the missing page.
On the following page is an example of the first few entries of a page
table. It is easy to see that page 0 is mapped to frame 23, page 1 is
mapped to frame 12, and page 3 is not in memory.
While this scheme seems simple, the implementation is rather com
plex. For each memory reference, the CPU must determine what page
is being referenced, find the proper entry in the page table, compute the
actual physical address by adding the offset to the frame’s location, and
finally perform the memory access. Two subtle problems emerge when
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